of the RHODOS microkernel (both hardware dependent and independent) that require design and development to allow multi-threading include areas such as: system stack management during interrupt and exception handling; allocation and control of microkernel resources; and context switching. To increase

or the whole space of potential er-ror traces is covered by causal loops. The causality-based verification of multi-threaded programs can be dramatically faster than the standard state space traversal. In particular, we show that the complexity of ver-ifying multi-threaded programs with locks reduces from

of applications to simultaneously schedule on the processor (workload), each application/thread must be assigned to one of the hardware contexts (strands). We call this last scheduling step the Thread to Strand Binding or TSB. In this paper, we show that the TSB impact on the performance of processors

-locate on the same processor threads that share data. The multi-thread sharing in the cache should reduce compulsory and invalidation misses, benefiting execution time. To test this hypothesis, we compared a variety of thread placement algorithms via trace-driven simulation of fourteen coarse- and medium

TITLE Generation of deterministic multi-threaded code from multiclock reactive programs

The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous Multi-Threaded (SMT) cores for general purpose systems. The most prominent use of such processors, at least in the near term, will be as job servers running multiple indepen-dent threads

of the application for linearizability at the level of user requests. This paper presents this technique for finding concurrency bugs, its application in the context of a testing tool that systematically searches for such problems, and our experience in applying our approach to MySQL, a large-scale complex multi-threaded

With the variables of a program classified as L (low, public) or H (high, private), the secure information flow problem is concerned with preventing the program from leaking information from H variables to L variables. In the context of a multi-threaded imperative language with probabilistic

-dependent preemption handling instruc-tions. The KEP3a compiler presented here is to our knowledge the first for multi-threaded reactive processors. The translation of Esterel’s preemption constructs onto KEP3a assembler is straightforward; however, a challenge is the correct and efficient representation of Esterel’s

Abstract Multithreaded architectures are emerging as an important class of parallel machines. By allowing fast context switching between threads on the same processor, these systems hide communication and synchronization latencies and allow scalable parallelism for dynamic and irregular