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150
Measuring the gap between fpgas and asics
- in ACM International Symposium on Field Programmable Gate Arrays
, 2006
"... This paper presents experimental measurements of the dif-ferences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better in-formed choices between ..."
Abstract
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Cited by 221 (6 self)
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required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain “hard ” blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC
Improvement of ASIC design processes
"... With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this context. The first is the estimation of man-months for a project, with the knowledge of the ASIC design flow that will be fo ..."
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With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this context. The first is the estimation of man-months for a project, with the knowledge of the ASIC design flow
A Methodology and Design Environment for DSP ASIC Fixed Point Refinement
, 1999
"... Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies ..."
Abstract
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Cited by 48 (1 self)
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for fixing MSB and LSB weights of fixed point signals. It enables short design cycles by combining the strengths of both analytical and simulation based methods. 1 Introduction Modern signal processing ASICs, such as integrated cable modems and wireless multimedia terminals, are specified with algorithms
I/O Buffer Placement Methodology for ASICs
- Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems, 2001
, 2001
"... In modern designs, voltage drop on the power grid is becoming a critical concern. One important technique to avoid severe voltage drops is to spread the highly power hungry buffers, such as I/O buffers, around the grid. In this paper, we study the problem of I/O buffer placement so as to avoid hot s ..."
Abstract
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Cited by 5 (0 self)
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In modern designs, voltage drop on the power grid is becoming a critical concern. One important technique to avoid severe voltage drops is to spread the highly power hungry buffers, such as I/O buffers, around the grid. In this paper, we study the problem of I/O buffer placement so as to avoid hot
ASIC Implementation of High Throughput PID Controller
"... Abstract- In this paper we implemented the pipelined Proportional Integral Derivative (PID) controller using the ASIC Implementation. We used Han Carlson adder and pipelined multiplier to design the PID controller which results into the implemented design can be useful to the modern controlling oper ..."
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Abstract- In this paper we implemented the pipelined Proportional Integral Derivative (PID) controller using the ASIC Implementation. We used Han Carlson adder and pipelined multiplier to design the PID controller which results into the implemented design can be useful to the modern controlling
Estimating Performance of a Ray-Tracing ASIC Design
"... Recursive ray tracing is a powerful rendering technique used to compute realistic images by simulating the global light transport in a scene. Algorithmic improvements and FPGA-based hardware implementations of ray tracing have demonstrated realtime performance but hardware that achieves performance ..."
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Cited by 6 (0 self)
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prototype clocked at 66 MHz achieves higher ray tracing performance than CPU-based ray tracers even on a modern multi-GHz CPU. We provide performance results for two 130nm ASIC versions and estimate what performance would be using a 90nm CMOS process. For a 90nm version with a 196mm 2 die we conservatively
ABSTRACT Measuring the Gap between FPGAs and ASICs
"... This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed choices between t ..."
Abstract
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to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain “hard ” blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4
Object-Oriented High-Level Modeling of an InfiniBand to PCI-X Bridge
"... The rapid increase in the complexity of modern ASICs raises the need for an increase in the abstraction level used to design these chips. While there exist many offerings of tools and languages designed to raise the level of abstraction in ASIC design, their use in current design is very limited. ..."
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The rapid increase in the complexity of modern ASICs raises the need for an increase in the abstraction level used to design these chips. While there exist many offerings of tools and languages designed to raise the level of abstraction in ASIC design, their use in current design is very limited.
Leakage power estimation for deep submicron circuits in an ASIC design environment,” DAC
, 2002
"... Static power dissipation due to leakage current in transistors constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the leakage contribution will increase rapidly. Developing power efficient products will require consider ..."
Abstract
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Cited by 16 (0 self)
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Static power dissipation due to leakage current in transistors constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the leakage contribution will increase rapidly. Developing power efficient products will require
1Buffer Design and Assignment Algorithm for Structured ASIC Optimization
"... In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insert ..."
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In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer
Results 1 - 10
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