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Table 4. Off-Chip Memory traffic line size cache On-Chip Memory total

in SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing
by Masaaki Kondo Research, Masaaki Kondo, Hideki Okawara, Taisuke Boku 2000
"... In PAGE 6: ... This explains why (b) and (c) are faster than (a) when mem- ory latency is 0 cycle. Table4 shows the traffic of Off- Chip Memory for each configurations. The third colum- n cache represents Off-Chip Memory traffic requested by cache, whereas the fourth column On-Chip Memo- ry represents traffic requested from On-Chip Memory.... In PAGE 7: ... The latency stall decreases for larger line size. However, as shown in Table4 , Off-Chip Memory traffic increases for larger cache line. In fact, through- put stall for 64B line is 1.... ..."
Cited by 3

Table 1: Off-chip data traffic reduced by ESP

in unknown title
by unknown authors 1997
"... In PAGE 3: ... We measured the aggregate miss traffic from the cache, and calculated the fraction of traffic that remained once write-backs and requests were elimi- nated. In Table1 , we show this measured fraction for fourteen of the SPEC95 benchmarks. We show both total traffic eliminated, and the reduction in the total number of distinct messages (we count a request/response pair as two transactions).... ..."
Cited by 66

Table 1: Off-chip data traffic reduced by ESP

in unknown title
by unknown authors 1997
"... In PAGE 3: ... We measured the aggregate miss traffic from the cache, and calculated the fraction of traffic that remained once write-backs and requests were elimi- nated. In Table1 , we show this measured fraction for fourteen of the SPEC95 benchmarks. We show both total traffic eliminated, and the reduction in the total number of distinct messages (we count a request/response pair as two transactions).... ..."
Cited by 66

Table 1: Off-chip data traffic reduced by ESP

in unknown title
by unknown authors 1997
"... In PAGE 3: ... We measured the aggregate miss traffic from the cache, and calculated the fraction of traffic that remained once write-backs and requests were elimi- nated. In Table1 , we show this measured fraction for fourteen of the SPEC95 benchmarks. We show both total traffic eliminated, and the reduction in the total number of distinct messages (we count a request/response pair as two transactions).... ..."
Cited by 66

Table 2 : Alternatives With Off-chip SRAM L COST 1

in Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks
by Aggelos Ioannou, Manolis, Manolis Katevenis 2001
Cited by 9

Table 2 : Alternatives With Off-chip SRAM L COST 1

in Pipelined heap (priority queue) management for advanced scheduling in high-speed networks
by Aggelos Ioannou, Manolis Katevenis 2001
Cited by 9

Table 1: Off-chip data traffic reduced by ESP

in unknown title
by unknown authors
"... In PAGE 3: ... We measured the aggregate miss traffic from the cache, and calculated the fraction of traffic that remained once write-backs and requests were eliminated. In Table1 , we show this measured fraction for fourteen of the SPEC95 benchmarks. We show both total traffic (megabytes) remaining, and the total number of distinct mes- sages remaining (we count a request/response pair as two transactions).... ..."

Table 1: Off-chip data traffic reduced by ESP

in Computer Sciences
by Stefanos Kaxiras, Doug Burger, James R. Goodman
"... In PAGE 3: ... We measured the aggregate miss traffic from the cache, and calculated the fraction of traffic that remained once write-backs and requests were eliminated. In Table1 , we show this measured fraction for fourteen of the SPEC95 benchmarks. We show both total traffic (megabytes) remaining, and the total number of distinct mes- sages remaining (we count a request/response pair as two transactions).... ..."

Table 3: Energy consumption of the on-chip and off-chip memory

in
by unknown authors
"... In PAGE 8: ... A detailed description of the models used was presented in [19, 20]. Table3 provides the energy consumption values of the used data memory modules. It can be easily seen that the total off-chip memory energy consumption (in J) is reduced around five times, while the total on-chip energy consump- tion (in mJ) is increased four times.... ..."

Table 4. Off-chip firmware accesses when sP sends a block of data.

in Micro-architectures of High Performance, Multi-user System Area Network Interface Cards
by Boon Seong Ang
"... In PAGE 7: ...5 processor clock (36 bus clocks). As shown in Table4 , when the sP sends block data, off-chip access occupies the sP bus for 34 bus clocks per packet. 6 Conclusions Our investigation shows that with innovative design, a firmware driven NIC built with off-the-shelf microproces- sor can deliver fairly competitive performance.... ..."
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