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PAML: a program package for phylogenetic analysis by maximum likelihood

by Ziheng Yang - COMPUT APPL BIOSCI 13:555–556 , 1997
"... PAML, currently in version 1.2, is a package of programs for phylogenetic analyses of DNA and protein sequences using the method of maximum likelihood (ML). The programs can be used for (i) maximum likelihood estimation of evolutionary parameters such as branch lengths in a phylogenetic tree, the tr ..."
Abstract - Cited by 1459 (17 self) - Add to MetaCart
among lineages (the molecular clock); (iii) calculation of sub-stitution rates at sites and reconstruction of ancestral nucleo-tide or amino acid sequences; and (iv) phylogenetic tree reconstruction by maximum likelihood and Bayesian methods.

A self-clocked fair queueing scheme for broadband applications

by S. Jamaloddin Golestani - Proceedings of IEEE INFOCOM’94 , 1994
"... A n ef ic ient fa i r queueing scheme which is feasi-ble f o r broadband implementation i s proposed and i ts performance i s analyzed. W e define fairness in a self-contained manner, eliminating the need f o r the hypo-thetical fluid-flow reference sys tem used in the present state of art and ther ..."
Abstract - Cited by 449 (0 self) - Add to MetaCart
, in the sense that the maximum permissible disparity among the normalized services offered to the backlogged ses-sions is newer more than two t imes the corresponding figure in any packet-based queueing system. 1

Dynamic Thermal Management for High-Performance Microprocessors

by David Brooks, Margaret Martonosi - In Proceedings of the 7th IEEE Symposium on High-Performance Computer Architecture , 2001
"... With the increasing clock rate and transistor count of today’s microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dyna ..."
Abstract - Cited by 333 (5 self) - Add to MetaCart
dynamic thermal management as a technique to control CPUpower dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip’s rated maximum power dissipation. However; system designers still must

Razor: A low-power pipeline based on circuit-level timing speculation

by Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, Trevor Mudge - in Proc. IEEE/ACM Int. Symp. Microarchitect , 2003
"... With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the ..."
Abstract - Cited by 288 (8 self) - Add to MetaCart
the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time

Maximum-Likelihood Models for Combined Analyses of Multiple Sequence Data

by Ziheng Yang - J. Mol. Evol , 1996
"... Models of nucleotide substitution were constructed for combined analyses of heterogeneous sequence data (such as those of multiple genes) from the same set of species. The models account for different aspects of the heterogeneity in the evolutionary process of different genes, such as differences in ..."
Abstract - Cited by 132 (16 self) - Add to MetaCart
in nucleotide frequencies, in substitution rate bias (for example, the transition /transversion rate bias), and in the extent of rate variation across sites. Model parameters were estimated by maximum likelihood and the likelihood ratio test was used to test hypotheses concerning sequence evolution

Start-time Fair Queuing: A Scheduling Algorithm for Integrated Services Packet Switching Networks

by Pawan Goyal, Harrick M. Vin, Haichen Cheng - In Proceedings of the ACM SIGCOMM '96 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication , 1996
"... We present Start-time Fair Queuing (SFQ) algorithm that is computationally efficient, achieves fairness regardless of variation in a server capacity, and has the smallest fairness measure among all known fair scheduling algorithms. We analyze its throughput, single server delay, and end-to-end delay ..."
Abstract - Cited by 191 (12 self) - Add to MetaCart
-to-end delay guarantee for variable rate Fluctuation Constrained (FC) and Exponentially Bounded Fluctuation (EBF) servers. We show that SFQ is better suited than Weighted Fair Queuing for integrated services networks and it is strictly better than Self Clocked Fair Queuing. To support heterogeneous services

Using Constraint Geometry to determine Maximum Rate Pipeline Clocking

by Chuan-hua Chang, Edward S. Davidson, Karem A. Sakallah - Proceedings of the International Conference on Computer-Aided Design , 1992
"... Abstract Geometric knowledge of the shape of the feasible region formed by pulse width, setup, and hold constraints, is used directly by a new efficient (cubic complexity) algorithm, Gpipe, to determine the maximum rate for single-phase clocking of a given pipeline. The pipeline model uses level-sen ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
Abstract Geometric knowledge of the shape of the feasible region formed by pulse width, setup, and hold constraints, is used directly by a new efficient (cubic complexity) algorithm, Gpipe, to determine the maximum rate for single-phase clocking of a given pipeline. The pipeline model uses level

Table 1. MAXIMUM RATINGS

by A V Dd, I Power, A Clk_out O Clock Output, C Clk_out O Clock Output
"... The NB3L02 is a low−skew, low jitter 1:2 clock fanout buffer, ideal for use in portable end−equipment, such as mobile phones or tablet applications. The MCLK_IN pin has an integrated AC coupling capacitor and will directly accept a square or sine wave clock input, such as a temperature compensated c ..."
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The NB3L02 is a low−skew, low jitter 1:2 clock fanout buffer, ideal for use in portable end−equipment, such as mobile phones or tablet applications. The MCLK_IN pin has an integrated AC coupling capacitor and will directly accept a square or sine wave clock input, such as a temperature compensated

Subthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance

by Muralidharan Venkatasubramanian, Vishwani D. Agrawal
"... Abstract — Evolving nanometer CMOS technologies provide low power, high performance and higher levels of integration but suffer from increased subthreshold leakage and excessive process variation. The present work examines the 45nm bulk and high-k technologies. We evaluate the performance of a 32-bi ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
-bit ripplecarry adder circuit for the entire range of supply voltages over which it displays correct function. Lowering voltage increases delay, reducing the maximum clock cycle rate. We use the maximum permissible clock rate and the energy per cycle at that clock rate as two performance criteria

An Optimal Internal Clock Synchronization Algorithm

by Christof Fetzer, Flaviu Cristian , 1995
"... We propose an optimal convergence function for achieving fault-tolerant, internal clock synchronization in the presence of arbitrary process and clock failures. The differential fault-tolerant midpoint convergence function guarantees an optimal maximum correction, an optimal maximum drift rate, and ..."
Abstract - Cited by 24 (1 self) - Add to MetaCart
We propose an optimal convergence function for achieving fault-tolerant, internal clock synchronization in the presence of arbitrary process and clock failures. The differential fault-tolerant midpoint convergence function guarantees an optimal maximum correction, an optimal maximum drift rate
Results 1 - 10 of 482