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2,165
PAML: a program package for phylogenetic analysis by maximum likelihood
- COMPUT APPL BIOSCI 13:555–556
, 1997
"... PAML, currently in version 1.2, is a package of programs for phylogenetic analyses of DNA and protein sequences using the method of maximum likelihood (ML). The programs can be used for (i) maximum likelihood estimation of evolutionary parameters such as branch lengths in a phylogenetic tree, the tr ..."
Abstract
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Cited by 1459 (17 self)
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among lineages (the molecular clock); (iii) calculation of sub-stitution rates at sites and reconstruction of ancestral nucleo-tide or amino acid sequences; and (iv) phylogenetic tree reconstruction by maximum likelihood and Bayesian methods.
Dynamic Thermal Management for High-Performance Microprocessors
- In Proceedings of the 7th IEEE Symposium on High-Performance Computer Architecture
, 2001
"... With the increasing clock rate and transistor count of today’s microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dyna ..."
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Cited by 333 (5 self)
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dynamic thermal management as a technique to control CPUpower dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip’s rated maximum power dissipation. However; system designers still must
Razor: A low-power pipeline based on circuit-level timing speculation
- in Proc. IEEE/ACM Int. Symp. Microarchitect
, 2003
"... With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the ..."
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Cited by 288 (8 self)
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the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time
clock
"... Spread-spectrum clock modulators reduce peak EMI in LCD panels Pin-selectable dither rate and magnitude reduce radiated emissions by up to 17dB An integrated phase-locked loop (PLL) modulates the output clock around the center frequency at a pinselectable magnitude, thus reducing peak EMI at fundame ..."
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Spread-spectrum clock modulators reduce peak EMI in LCD panels Pin-selectable dither rate and magnitude reduce radiated emissions by up to 17dB An integrated phase-locked loop (PLL) modulates the output clock around the center frequency at a pinselectable magnitude, thus reducing peak EMI
The reaction of household consumption to predictable changes in social security taxes.”American Economic Review
, 1999
"... This paper evaluates the key implication of rational expectations and the basic Life Cycle/Permanent Income Hypothesis (LCH/PIH): that predictable changes in income have no e®ect on the growth rate of consumption expenditures. 1 This implication is important for understanding the e®ectiveness and op ..."
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Cited by 229 (12 self)
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This paper evaluates the key implication of rational expectations and the basic Life Cycle/Permanent Income Hypothesis (LCH/PIH): that predictable changes in income have no e®ect on the growth rate of consumption expenditures. 1 This implication is important for understanding the e
Dynamic IPC/Clock Rate Optimization
- PROCEEDINGS OF THE 25TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
, 1998
"... Current microprocessor designs set the functionality and clock rate of the chip at design time based on the configuration that achieves the best overall performance over a range of target applications. The result may be poor performance when running applications whose requirements are not well-match ..."
Abstract
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Cited by 86 (19 self)
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Current microprocessor designs set the functionality and clock rate of the chip at design time based on the configuration that achieves the best overall performance over a range of target applications. The result may be poor performance when running applications whose requirements are not well
Maximum-Likelihood Models for Combined Analyses of Multiple Sequence Data
- J. Mol. Evol
, 1996
"... Models of nucleotide substitution were constructed for combined analyses of heterogeneous sequence data (such as those of multiple genes) from the same set of species. The models account for different aspects of the heterogeneity in the evolutionary process of different genes, such as differences in ..."
Abstract
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Cited by 132 (16 self)
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in nucleotide frequencies, in substitution rate bias (for example, the transition /transversion rate bias), and in the extent of rate variation across sites. Model parameters were estimated by maximum likelihood and the likelihood ratio test was used to test hypotheses concerning sequence evolution
Start-time Fair Queuing: A Scheduling Algorithm for Integrated Services Packet Switching Networks
- In Proceedings of the ACM SIGCOMM '96 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication
, 1996
"... We present Start-time Fair Queuing (SFQ) algorithm that is computationally efficient, achieves fairness regardless of variation in a server capacity, and has the smallest fairness measure among all known fair scheduling algorithms. We analyze its throughput, single server delay, and end-to-end delay ..."
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Cited by 191 (12 self)
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-to-end delay guarantee for variable rate Fluctuation Constrained (FC) and Exponentially Bounded Fluctuation (EBF) servers. We show that SFQ is better suited than Weighted Fair Queuing for integrated services networks and it is strictly better than Self Clocked Fair Queuing. To support heterogeneous services
Estimating Clock Uncertainty for Efficient Duty-Cycling in Sensor Networks
"... Radio duty cycling has received significant attention in sensor networking literature, particularly in the form of protocols for medium access control and topology management. While many protocols have claimed to achieve significant dutycycling benefits in theory and simulation, these benefits have ..."
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Cited by 64 (7 self)
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. This paper proposes an uncertainty-driven approach to duty-cycling, where a model of long-term clock drift is used to minimize the dutycycling overhead. First, we use long-term empirical measurements to evaluate and analyze in-depth the interplay between three key parameters that influence long
Understanding Retiming through Maximum Average-Delay Cycles
- Mathematical Systems Theory
, 1994
"... A synchronous circuit built of functional elements and registers is a simple implementation of the semisystolic model of computation that can be used to design parallel algorithms. Retiming is a well-known technique that transforms a given circuit into a faster circuit by relocating its registers. W ..."
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Cited by 38 (9 self)
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. We give tight bounds on the minimum clock period that can be achieved by retiming a synchronous circuit. These bounds are expressed in terms of the maximum delay-to-register ratio of the cycles in the circuit graph and the maximum propagation delay d max of the circuit components. Our bounds do
Results 1 - 10
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