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Table 3. Synthesis results (for SHA-256, AES, SHA-1) and estimations (MD5, MD4) of hash functions and AES algorithm implementations for low die-size and low power consumption
2006
"... In PAGE 9: ... In addition to being the smallest published ASIC implementation of SHA-256 our low-power approach allows application of SHA-256 in RFID system with minimal reduction of the operation range. 4 Discussion of Implications Table3 presents a comparison of four hash function implementations with the AES implementation of Feldhofer [6]. The figures of the SHA-256 and SHA-1 implementations are synthesis results while for MD5 and MD4 only estimations are available.... ..."
Cited by 11
Table 5.5: Synthesis results and estimations of hash functions and AES algorithm implemen- tations for low die-size and low power consumption Algorithm Chip area
2006
Table 1: Comparison of hardware cost and power consumption of the logarithmic low-power DCT architecture with other approaches.
1995
"... In PAGE 6: ...5 frequency at the nal stage, we need a total of (log M +2) multipliers to realize the multirate transfer function. The comparison of the logarithmic low-power architecture with other approaches is listed in Table1 . Although the total power savings of the logarithmic structure is less than that of the full multirate structure given the same decimation factor M, the O(log M) hardware overhead is preferable when we want to achieve low-power consumption without trading too much chip area.... ..."
Cited by 1
Table 1 AREA AND POWER CONSUMPTION OF BENCHMARK CIRCUITS FOR EACH LOW POWER SCHEME
"... In PAGE 4: ... In DIFFEQ example, the three low power schemes gradually decrease power consumption. But in ELLIP example where storage power consumption is dominant as we can see in Table1 , PPM scheme increases power consumption by using more storage elements than the original circuit. In any cases circuit implementation with latches consumes less power compared to the circuit with other power management schemes.... ..."
Table 5: Comparison of 802.11 and a low power radio device energy consumption figures
Table 1: Power consumption of commercially available low-power transceivers RFM TR1001 [10] ChipCon CC1100 [1] Nordic nRF905 [8]
2006
"... In PAGE 2: ...1 Challenges for WSN MAC protocols In the recent state of technology, the RF transceiver consumes most energy in the sensor node architecture. Low-power transceivers, suitable for this architecture, consume typically in receiving or transmitting state in the order of 30mW and in standby state less than 30 W ( Table1 ). Thus, a reasonable battery of 1Ah allows for 100 hours of continuous transmitting or receiving (excluding any other component of the wireless sensor node) and roughly 11 years of being in standby mode.... ..."
Table II. Operating Frequency and Power Consumption Ratios (between a Low power ARM7 processor, a traditional FPGA, and the W-FPGA) Device Proc.:FPGA Freq. Proc.:FPGA Power
2006
Cited by 5
Table 2: Test length and fault coverage comparison Regarding the above results, it should be noted that the fault coverage obtained with a standard BIST scheme is not affected by the proposed low power BIST scheme. The fault coverage is roughly the same as that obtained with a classical LFSR, with a test length which is most of the time decreased compared with the test length in a standard BIST scheme. Now, results about the power and energy savings achieved by the proposed low power BIST scheme are discussed. Power consumption in each circuit was estimated by using PowerMill,
2001
"... In PAGE 10: ... The goal of the experiments we performed has been first to make sure that the main test parameters (test length and fault coverage) keep the same values under the new low power BIST scheme, and next to measure the power and energy savings that our solution allows to obtain on the CUT, the TPG and the clock tree. First, results of the proposed low power BIST technique in terms of test length and fault coverage are reported in Table2 . All experiments are based on pseudo-random pattern testing, and complete fault coverage cannot be expected for each circuit.... In PAGE 10: ... This information is listed in the second and third columns. In the second part of Table2 , the same results (test length and fault coverage) obtained with the proposed low power TPG are given for each benchmark circuit. The polynomials for all the LFSRs were chosen from a set of primitive polynomials under the constraint to provide the highest fault coverage.... ..."
Table 2 shows the power analysis of different low power programmable cores with a generic multiplier. It is evident from the results that the power consumption of the combined core (combination of both block processing and segmentation techniques) has the lowest value (61% power saving). This saving is due to the maximum reduction in switching activity at multiplier input, due to the combination of both, block processing architecture and coefficient segmentation architecture. Because of this low switching activity in this architecture, the total power is 8mW and a power saving of 61% is achieved.
"... In PAGE 4: ...1 Power Results Tables 2, 3 and 4 shows the power result of programmable low power FIR filter cores with three different types of multipliers. Table2 : Power analysis with generic multiplier ... ..."
Table 3: Low power logic synthesis results It is pertinent to note that the system power consumption problem also encompasses chipsets, i.e., devices such as the memory, I/O, and graphics controllers. These operate at a fraction of the CPU clock frequency, and large portions of these are well-suited to be implemented as ASICs. Low power synthesis thus has a much larger impact in this domain.
1998
Cited by 55
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