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Table 4. Cost of the matrix step for the large matrix
2002
"... In PAGE 22: ...ake high bandwidth inter-wafer connections (cf. 5.3). Using the formulas given in the previous section, we obtain the costs in Table4 for the custom and FPGA implementations, for various parameter choices. The third line shows that here too, significant parallelism can be attained at very little cost (88% of the wafer area is occupied by DRAM storing the input).... ..."
Cited by 7
Table 4. Cost of the matrix step for the large matrix
2002
Cited by 7
Table 2. Communication pattern for row-based partitioning of the pig-large matrix on 16 processors.
1998
"... In PAGE 6: ...66 137 31709 15 7312 The 28; 254 17; 284 pig-large matrix [5, 9] with 75,018 nonzeros arises from a least squares problems. The multilevel methods (see Table2 ) are best, reducing the edge cuts, total message volume, and the processor message volume by factors of more than three in every case. The 6; 071 12; 230 dfl001 matrix3 with 35,632 nonzeros arises from linear programming.... ..."
Cited by 4
Table 6.3 Communication pattern for row-based partitioning of the pig-large matrix on eight processors.
2000
Cited by 15
Table 6.4 Block information for the row-based partitioning of the pig-large matrix on eight processors.
2000
Cited by 15
Table 6.3 Communication pattern for row-based partitioning of the pig-large matrix on 8 processors.
2000
Cited by 15
Table 6.4 Block information for the row-based partitioning of the pig-large matrix on 8 processors.
2000
Cited by 15
Table 6.3 Communication pattern for row-based partitioning of the pig-large matrix on eight processors.
2000
Cited by 15
Table 6.4 Block information for the row-based partitioning of the pig-large matrix on eight processors.
2000
Cited by 15
Table 6.3 Communication pattern for row-based partitioning of the pig-large matrix on eight processors.
Cited by 4
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