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8,108
Efficient retiming of large circuits
- IEEE TRANS VLSI
, 1998
"... Retiming, introduced by Leiserson and Saxe, is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization and also presented a fast algo ..."
Abstract
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Cited by 28 (1 self)
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of handling large circuits in a reasonable time. This work defines the relationship between the Leiserson–Saxe and the ASTRA approaches and utilizes it for efficient minarea retiming of large circuits. The new algorithm, Minaret, uses the same basis as the Leiserson–Saxe approach. The underlying philosophy
Wattch: A Framework for Architectural-Level Power Analysis and Optimizations
- In Proceedings of the 27th Annual International Symposium on Computer Architecture
, 2000
"... Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high ..."
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Cited by 1320 (43 self)
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Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve
The University of Florida sparse matrix collection
- NA DIGEST
, 1997
"... The University of Florida Sparse Matrix Collection is a large, widely available, and actively growing set of sparse matrices that arise in real applications. Its matrices cover a wide spectrum of problem domains, both those arising from problems with underlying 2D or 3D geometry (structural enginee ..."
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Cited by 536 (17 self)
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The University of Florida Sparse Matrix Collection is a large, widely available, and actively growing set of sparse matrices that arise in real applications. Its matrices cover a wide spectrum of problem domains, both those arising from problems with underlying 2D or 3D geometry (structural
Boosting a Weak Learning Algorithm By Majority
, 1995
"... We present an algorithm for improving the accuracy of algorithms for learning binary concepts. The improvement is achieved by combining a large number of hypotheses, each of which is generated by training the given learning algorithm on a different set of examples. Our algorithm is based on ideas pr ..."
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Cited by 516 (16 self)
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We present an algorithm for improving the accuracy of algorithms for learning binary concepts. The improvement is achieved by combining a large number of hypotheses, each of which is generated by training the given learning algorithm on a different set of examples. Our algorithm is based on ideas
Real-Time Computing Without Stable States: A New Framework for Neural Computation Based on Perturbations
"... A key challenge for neural modeling is to explain how a continuous stream of multi-modal input from a rapidly changing environment can be processed by stereotypical recurrent circuits of integrate-and-fire neurons in real-time. We propose a new computational model for real-time computing on time-var ..."
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Cited by 469 (38 self)
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be implemented on generic evolved or found recurrent circuitry. It is shown that the inherent transient dynamics of the high-dimensional dynamical system formed by a sufficiently large and heterogeneous neural circuit may serve as universal analog fading memory. Readout neurons can learn to extract in real
Large Circuits in Binary Matroids of Large Cogirth: I
"... Let F 7 denote the Fano matroid and e be a fixed element of F 7 . Let P (F 7 ; e) be the family of matroids obtained by taking the parallel connection of one or more copies of F 7 about e. Let M be a simple binary matroid such that every cocircuit of M has size at least d 3. We show that if M d ..."
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Cited by 2 (0 self)
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does not have an F 7 -minor, M 6= F 7 and d (r(M) + 1)=2 then M has a circuit of size r(M) + 1. We also show that if M is connected, e 2 E(M ), M does not have both an F 7 -minor and an F 7 -minor, and M = 2 P (F 7 ; e), then M has a circuit that contains e and has size at least d + 1.
Partitioning very large circuits using analytical placement techniques
- in Proceedings 31st ACM/IEEE Design Automation Conference
, 1994
"... A new partitioning approach for very large circuits is described. We demonstrate that applying a recently developed analytical placement algorithm, that pro ts from a linear objective function, signi cantly improves the partitioning quality compared to the well-known eigenvector approach, which mini ..."
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Cited by 42 (2 self)
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A new partitioning approach for very large circuits is described. We demonstrate that applying a recently developed analytical placement algorithm, that pro ts from a linear objective function, signi cantly improves the partitioning quality compared to the well-known eigenvector approach, which
Generation of very large circuits to benchmark the partitioning of FPGA
- In ISPD '99: Proceedings of the 1999 International Symposium on Physical Design
, 1999
"... This paper describes a new procedure for generating very large realistic benchmark circuits which are especially suited for the performance evaluation of FPGA partitioning algorithms. These benchmark circuits can be generated quickly. The generation of a netlist of 100K CLBs (500K equivalent gates), ..."
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Cited by 14 (0 self)
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This paper describes a new procedure for generating very large realistic benchmark circuits which are especially suited for the performance evaluation of FPGA partitioning algorithms. These benchmark circuits can be generated quickly. The generation of a netlist of 100K CLBs (500K equivalent gates
The Case for a Single-Chip Multiprocessor
- IEEE Computer
, 1996
"... Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we look for new ways to use their capabilities effectively. This paper shows that in advanced technologies it is possible to ..."
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Cited by 440 (6 self)
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Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we look for new ways to use their capabilities effectively. This paper shows that in advanced technologies it is possible
Fast Computation of Substrate Resistances in Large Circuits
, 1996
"... In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract ..."
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Cited by 11 (0 self)
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In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract
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