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Table 2: Subset of design space explored

in Intelligent Gradient-Based Search of Incompletely Defined Design Spaces
by Mark Schwabacher, Andrew Gelsey 1996
"... In PAGE 13: ... If the design parameters were independent in this second sense, then they could be optimized one at a time, which would be much less expensive. Table2 shows the subset we explored in the design space de ned by these eight design parameters. We compared four optimization strategies: Plain CFSQP: In this strategy, unevaluable points are replaced with a standard \very bad value quot; which is passed to the optimizer, CFSQP, and to the gradient routine, which computes gradients using the standard central-di erence formula.... ..."
Cited by 8

Table 3: DTMF level design space exploration

in Truly Rapid Prototyping Requires High-Level Synthesis
by Goran Doncev, Miriam Leeser, Shantanu Tarafdar
"... In PAGE 16: ... By unrolling the inner loop, we overlap the execution of four stages. Table3 shows the results from the design space exploration of the complete DTMF receiver. Each row presents the results for one of the four implementations described above.... In PAGE 17: ...Table 3: DTMF level design space exploration The rst row in Table3 shows the results for the implementation when the loop is kept rolled. This is the fastest design and takes 222 cycles (44:00 sec) to process each input sample.... In PAGE 17: ... Its inputs are 5-bit wide and it has an 8-bit output. The comparators and adder/subtracters indicated in Table3 are the ones used to process the input samples. Their inputs and outputs are 12-bit, except for the comparator output which is 1-bit.... In PAGE 18: ... This may result in an increase in area, but the resulting design should easily t onto two Altera chips. 641 566 600 655 655 696 702 653 5168 Estimated Area after running BC Stage_697 Stage_770 Stage_842 Stage_951 Stage_1209 Stage_1336 Stage_1477 Stage_1633 Total Table 4: Area estimates for each stage The second row in Table3 shows the results of the implementation obtained when the loop was unrolled. This implementation is slower and bigger than the previous one.... ..."

Table 1: Feature comparison of design space exploration tools.

in Methods for Evaluating and Covering the Design Space during Early Design Development
by Matthias Gries 2004
Cited by 21

Table 1. Parameters of architectures consid- ered in our Design Space Exploration

in Using predictive modeling for cross-program design space exploration in multicore systems
by Salman Khan, Polychronis Xekalakis, John Cavazos, Marcelo Cintra 2007
"... In PAGE 6: ... More specifically, we look into different branch prediction sizes, issue/rename/commit widths, re- order buffer sizes, window and load-store queue size, differ- ent numbers of L1 and L2 miss handling registers (MSHR) and different register file sizes. The detailed values for the parameters we varied can be seen in Table1 . We choose not to vary the instruction cache parameters, because our appli- cations have very small instruction miss-rates and even sub- optimal configurations did not affect their performance.... ..."
Cited by 1

Table 1: Design space exploration by means of plotted metrics Structure

in unknown title
by unknown authors

Table 8: Benchmarks for design space exploration. Name Workload Memory Footprint

in Embedded Memory Systems
by Dr. Krisha Palem Advisor, Dr. Santosh Pande, Dr. Yannis Smaragdakis 2006

Table 1 Feature comparison of design space exploration tools: System-level frameworks. Name Application

in Methods for Evaluating and Covering the Design Space during Early Design Development
by Matthias Gries 2004
"... In PAGE 48: ...Comparison The features of the mentioned tools are summarized in Table1 to 3. Tools focused on system-level design allow the designer to express heterogeneous multi-processor systems.... ..."
Cited by 21

Table 1 Feature comparison of design space exploration tools: System-level frameworks. Name Application

in Methods for Evaluating and Covering the Design Space during Early Design Development
by Matthias Gries 2004
"... In PAGE 47: ... 6.4 Comparison The features of the mentioned tools are summarized in Table1 to 3. Tools focused on system-level design allow to express heterogeneous multi-processor systems.... ..."
Cited by 21

Table 2 Feature comparison of design space exploration tools: Micro-architecture. Name Application

in Methods for Evaluating and Covering the Design Space during Early Design Development
by Matthias Gries 2004
Cited by 21

Table 3 Feature comparison of design space exploration tools: related frameworks. Name Application

in Methods for Evaluating and Covering the Design Space during Early Design Development
by Matthias Gries 2004
Cited by 21
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