-correlating prefetcher that keeps predictor meta-data in main memory while achieving 90 % of the performance potential of idealized on-chip meta-data storage. 1.

for fast access and practical on-chip dedicated storage. Depending on the application, these requirements are at odds. For example, commercial applications that exhibit large instruction footprints benefit from large BTBs. This work introduces a new BTB design that accommodates large instruction footprints

ABSTRACT Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power

for an idealized prefetcher that over-approximates the STMS prefetcher, the previous best tem-poral stream prefetcher; this ISB prefetcher uses 32 KB of on-chip storage and sees 8.4 % memory traffic overhead due to meta-data accesses. We also show that a hybrid prefetcher that combines a stride

Abstract: The fabrication of 3-d nanostructures can serve as building blocks for a vast range of on-chip energy storage devices. The ability to precisely control material deposition inside these structures is attractive due to its potential for integration with conventional fabrication technology

have targeted optimized router buffer design. In this paper, we propose iDEAL- inter-router, dual-function energy and area-efficient links capa-ble of data transmission as well as data storage when required. iDEAL enables a reduction in the router buffer size by control-ling the repeaters along

New designs for petabyte-scale storage systems are now capable of transferring hundreds of gigabytes of data per second, but lack strong security. We propose a scalable and efficient protocol for security in high performance, objectbased storage systems that reduces protocol overhead and eliminates

Flash-based solid-state drives have revolutionized stor-age with their high performance. Their sophisticated in-ternal mechanisms have led to a plethora of research on how to optimize applications, file systems, and internal SSD designs. Due to the closed nature of commercial de-vices though, most

for recently accessed rows on-chip using a small buffer. Leveraging the flexibility and efficiency of such a fine-granularity DRAM cache, we also develop an adaptive policy to choose the best granularity when migrating data into DRAM. On a hybrid memory with a 512MB DRAM cache, our proposal using an 8KB on-chip

at the current status of available technology for long term data storage, more specific the standards that exist for data interchange, the creation and storage of metadata, data conversion problems and the reliability and suitability of digital storage media. Even if in the ideal for-mat, application