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9,185
Low-Power CMOS Digital Design
- JOURNAL OF SOLID-STATE CIRCUITS. VOL 27, NO 4. APRIL 1992 413
, 1992
"... Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the ..."
Abstract
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Cited by 580 (20 self)
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Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use
Subthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance
"... Abstract — Evolving nanometer CMOS technologies provide low power, high performance and higher levels of integration but suffer from increased subthreshold leakage and excessive process variation. The present work examines the 45nm bulk and high-k technologies. We evaluate the performance of a 32-bi ..."
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Cited by 1 (0 self)
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Abstract — Evolving nanometer CMOS technologies provide low power, high performance and higher levels of integration but suffer from increased subthreshold leakage and excessive process variation. The present work examines the 45nm bulk and high-k technologies. We evaluate the performance of a 32
Data networks
, 1992
"... a b s t r a c t In this paper we illustrate the core technologies at the basis of the European SPADnet project (www. spadnet.eu), and present the corresponding first results. SPADnet is aimed at a new generation of MRI-compatible, scalable large area image sensors, based on CMOS technology, that are ..."
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Cited by 2210 (5 self)
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a b s t r a c t In this paper we illustrate the core technologies at the basis of the European SPADnet project (www. spadnet.eu), and present the corresponding first results. SPADnet is aimed at a new generation of MRI-compatible, scalable large area image sensors, based on CMOS technology
System architecture directions for networked sensors
- IN ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS
, 2000
"... Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. They can be deeply embedded in the physical world or spread throughout our environment. The missing elements are an overall system architecture and a methodo ..."
Abstract
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Cited by 1789 (58 self)
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Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. They can be deeply embedded in the physical world or spread throughout our environment. The missing elements are an overall system architecture and a
Modeling the effect of technology trends on the soft error rate of combinational logic
, 2002
"... This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. Th ..."
Abstract
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Cited by 374 (8 self)
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This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs
Gate dielectric scaling for high-performance CMOS: from SiO2 to High-K
- In IWGI, 2003. 84
, 2004
"... We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45nm high-performance logic technology node. 1. ..."
Abstract
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Cited by 12 (0 self)
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We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45nm high-performance logic technology node. 1.
Single-pixel imaging via compressive sampling
- IEEE Signal Processing Magazine
"... Humans are visual animals, and imaging sensors that extend our reach – cameras – have improved dramatically in recent times thanks to the introduction of CCD and CMOS digital technology. Consumer digital cameras in the mega-pixel range are now ubiquitous thanks to the happy coincidence that the semi ..."
Abstract
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Cited by 296 (19 self)
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Humans are visual animals, and imaging sensors that extend our reach – cameras – have improved dramatically in recent times thanks to the introduction of CCD and CMOS digital technology. Consumer digital cameras in the mega-pixel range are now ubiquitous thanks to the happy coincidence
CMOS Development and Optimization, Scaling Issue and Replacement with High-k Material for Future Microelectronics
"... been guided by CMOS scaling theory [1] and predications made by Semiconductor Industry (SIA) in the International Technology Roadmap for Semiconductor (ITRS). With the trend of scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistor as Moore’s Law [2] requires replacement of conven ..."
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principle of physics. Here we have elaborated about scaling issues and alternate high-k dielectric for Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Introducing a high-k material may replace today’s silicon dioxide technology and can also provide extendibility over several generations. C
Low Power CMOS Digital Design
- IEEE JOURNAL OF SOLID STATE CIRCUITS
, 1995
"... Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the ..."
Abstract
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Cited by 146 (0 self)
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Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use
Bus-invert coding for low-power I/O
- IEEE TRANS. VLSI SYST
, 1995
"... Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). ..."
Abstract
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Cited by 222 (5 self)
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Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period
Results 1 - 10
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9,185
