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32,984
Design of an Optimal Loosely Coupled Heterogeneous Multiprocessor System
- Proc. ED&TC
, 1996
"... This paper presents an approach for mapping tasks optimal to hardware and software components in order to design a real-time system. The tasks are derived from an algorithm and are represented by a task-graph. The performance of the algorithm on the resulting real-time system will meet the specified ..."
Abstract
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Cited by 28 (0 self)
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and loosely coupled multiprocessor system, which violates no timing constraints while performing the underly...
MILP Based Task Mapping for Heterogeneous Multiprocessor Systems
- in Proceedings European Design Automation Conference
, 1996
"... CAD-systems supporting hardware/software codesign map different tasks of an algorithm onto processors. Some of the processors are programmable and others are application specific. We propose a new MILP (mixed integer linear program) model that allows to determine a mapping optimizing a trade off fun ..."
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Cited by 29 (0 self)
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CAD-systems supporting hardware/software codesign map different tasks of an algorithm onto processors. Some of the processors are programmable and others are application specific. We propose a new MILP (mixed integer linear program) model that allows to determine a mapping optimizing a trade off
Design Methodology for Pipelined Heterogeneous Multiprocessor System
, 2007
"... Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g. SMP) and application specific architectures (i.e. DSP, ASIC). ASIPs have emerged as a viable alternative to conve ..."
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Cited by 17 (4 self)
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to conventional processing entities (PEs) due to its configurability and programmability. In this work, we introduce a heterogeneous multi-processor system using ASIPs as processing entities in a pipeline configuration. A streaming application is taken and manually broken into a series of algorithmic stages (each
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
- in Proceedings of the Design Automation and Test in Europe (DATE
, 2003
"... In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous processors is how to maintain the coherence of data caches. In this paper, we propose a hardware/software methodology to ..."
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Cited by 9 (3 self)
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In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous processors is how to maintain the coherence of data caches. In this paper, we propose a hardware/software methodology
Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG
- INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING
, 2007
"... Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive realti ..."
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Cited by 3 (0 self)
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Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive
Voltage Reduction of Application-Specific Heterogeneous Multiprocessor Systems for Power
"... Abstract — We present a design strategy to reduce power demands in application-specific, heterogeneous multiprocessor systems with interdependent subtasks. This power reduction scheme can be used with a randomised search such as a genetic algorithm where multiple trial solutions are tested. The sche ..."
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Abstract — We present a design strategy to reduce power demands in application-specific, heterogeneous multiprocessor systems with interdependent subtasks. This power reduction scheme can be used with a randomised search such as a genetic algorithm where multiple trial solutions are tested
Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures
"... www12.cs.fau.de We present the prototyping of a heterogeneous multiprocessor system-on-chip (MPSoC) design, which consists of general purpose RISC processors as well as novel accelerators in form of tightly-coupled processor arrays (TCPA). In general, TCPAs are well suited to accelerate numerous com ..."
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www12.cs.fau.de We present the prototyping of a heterogeneous multiprocessor system-on-chip (MPSoC) design, which consists of general purpose RISC processors as well as novel accelerators in form of tightly-coupled processor arrays (TCPA). In general, TCPAs are well suited to accelerate numerous
Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip
- Proc. of DAC 2001
, 2001
"... We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level system specification. Parameters are used to instantiate architectural components, such as processors, memory modules and comm ..."
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Cited by 59 (12 self)
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We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level system specification. Parameters are used to instantiate architectural components, such as processors, memory modules
Co-Synthesis of Heterogeneous Multiprocessor Systems Using Arbitrated Communication
- Proceeding of the 1999 International Conference on CAD
, 1999
"... : We describe the #rst co-design technique aimed at heterogeneous systems employing arbitrated communication. The method cleanly divides the co-design problem into two parts: an outer-loop which enumerates a series of hardware con#gurations upon which the inner-loop attempts to determines schedu ..."
Abstract
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Cited by 11 (2 self)
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schedule feasibility. This framework is used for co-design of single-bus, heterogeneous multi-processor realtime systems which use arbitrated communication. Arbitrated system design is especially di#cult because communication scheduling is directly tied to task allocation. Allocation, in turn
Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip
"... Increasingly more MPSoC platforms are being developed to meet the rising demands from concurrently executing applications. These systems are often heterogeneous with the use of dedicated IP blocks and application domain specific processors. While there is a host of research done to provide good perf ..."
Abstract
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Cited by 9 (3 self)
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Increasingly more MPSoC platforms are being developed to meet the rising demands from concurrently executing applications. These systems are often heterogeneous with the use of dedicated IP blocks and application domain specific processors. While there is a host of research done to provide good
Results 1 - 10
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32,984
