Results 1 - 10
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10,514
Configurable Motion-Estimation Hardware Accelerator Module for the MPEG-4 Reference Hardware Description Platform
- IEEE International Conference On Image Processing (ICIP05
, 2005
"... This paper describes a motion estimation co-processor architecture that explicitly separates the implementation stages consisting of data access to the search window and the evaluation of the matching criterion from the implementation of the search strategy. The architecture is modular and can be re ..."
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Cited by 7 (6 self)
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architectures supporting mixed SW/HW implementations of video encoders such as generic PC platforms with a standard PCMCIA FPGA cards. The module has been developed in the framework of the MPEG reference hardware description activity.
Efficient Software-Based Fault Isolation
, 1993
"... One way to provide fault isolation among cooperating software modules is to place each in its own address space. However, for tightly-coupled modules, this solution incurs prohibitive context switch overhead, In this paper, we present a software approach to implementing fault isolation within a sing ..."
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Cited by 777 (12 self)
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modules. We demonstrate that for frequently communicating modules, implementing fault isolation in software rather than hard-ware can substantially improve end-to-end application performance.
Telos: Enabling Ultra-Low Power Wireless Research
, 2005
"... We present Telos, an ultra low power wireless sensor module (“mote”) for research and experimentation. Telos is the latest in a line of motes developed by UC Berkeley to enable wireless sensor network (WSN) research. It is a new mote design built from scratch based on experiences with previous mote ..."
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Cited by 717 (21 self)
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We present Telos, an ultra low power wireless sensor module (“mote”) for research and experimentation. Telos is the latest in a line of motes developed by UC Berkeley to enable wireless sensor network (WSN) research. It is a new mote design built from scratch based on experiences with previous mote
Towards an Active Network Architecture
- Computer Communication Review
, 1996
"... Active networks allow their users to inject customized programs into the nodes of the network. An extreme case, in which we are most interested, replaces packets with "capsules" -- program fragments that are executed at each network router/switch they traverse. Active architectures permit ..."
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Cited by 497 (7 self)
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, they will accelerate the pace of innovation by decoupling network services from the underlying hardware and allowing new services to be loaded into the infrastructure on demand. In this paper, we describe our vision of an active network architecture, outline our approach to its design, and survey the technologies
Dynamo: A Transparent Dynamic Optimization System
- ACM SIGPLAN NOTICES
, 2000
"... We describe the design and implementation of Dynamo, a software dynamic optimization system that is capable of transparently improving the performance of a native instruction stream as it executes on the processor. The input native instruction stream to Dynamo can be dynamically generated (by a JIT ..."
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Cited by 479 (2 self)
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native binaries can be accelerated Dynamo, and often by a significant degree. For example, the average performance of --O optimized SpecInt95 benchmark binaries created by the HP product C compiler is improved to a level comparable to their --O4 optimized version running without Dynamo. Dynamo achieves
The Paradyn Parallel Performance Measurement Tools
- IEEE COMPUTER
, 1995
"... Paradyn is a performance measurement tool for parallel and distributed programs. Paradyn uses several novel technologies so that it scales to long running programs (hours or days) and large (thousand node) systems, and automates much of the search for performance bottlenecks. It can provide precise ..."
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Cited by 447 (39 self)
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. The instrumentation is controlled by the Performance Consultant module, that automatically directs the placement of instrumentation. The Performance Consultant has a well-defined notion of performance bottlenecks and program structure, so that it can associate bottlenecks with specific causes and specific parts of a
On the Design and Development of Program families
, 1976
"... Program families are defined (analogously to hardware families) as sets of programs whose common properties are so extensive that it is advantageous to study thecommon properties of the programs before analyzing individual members. The assumption that, ifone is to develop a set of similar programs o ..."
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Cited by 326 (5 self)
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Program families are defined (analogously to hardware families) as sets of programs whose common properties are so extensive that it is advantageous to study thecommon properties of the programs before analyzing individual members. The assumption that, ifone is to develop a set of similar programs
High-Quality Pre-Integrated Volume Rendering Using Hardware-Accelerated Pixel Shading
, 2001
"... We introduce a novel texture-based volume rendering approach that achieves the image quality of the best post-shading approaches with far less slices. It is suitable for new flexible consumer graphics hardware and provides high image quality even for low-resolution volume data and non-linear transfe ..."
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Cited by 246 (22 self)
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We introduce a novel texture-based volume rendering approach that achieves the image quality of the best post-shading approaches with far less slices. It is suitable for new flexible consumer graphics hardware and provides high image quality even for low-resolution volume data and non
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling
- in Proceedings of the 30th annual international symposium on Computer architecture
, 2003
"... Current software-based microarchitecture simulators are many orders of magnitude slower than the hardware they simulate. Hence, most microarchitecture design studies draw their conclusions from drastically truncated benchmark simulations that are often inaccurate and misleading. This paper presents ..."
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Cited by 258 (25 self)
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Current software-based microarchitecture simulators are many orders of magnitude slower than the hardware they simulate. Hence, most microarchitecture design studies draw their conclusions from drastically truncated benchmark simulations that are often inaccurate and misleading. This paper presents
Small vision system: Hardware and implementation
- Proc. of the Intl. Symp. of Robotics Research (ISRR
, 1997
"... Robotic systems are becoming smaller, lower power, and cheaper, enabling their application in areas not previously considered. This is true of vision systems as well. SRI’s Small Vision Module (SVM) is a compact, inexpensive realtime device for computing dense stereo range images, which are a fundam ..."
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Cited by 206 (14 self)
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Robotic systems are becoming smaller, lower power, and cheaper, enabling their application in areas not previously considered. This is true of vision systems as well. SRI’s Small Vision Module (SVM) is a compact, inexpensive realtime device for computing dense stereo range images, which are a
Results 1 - 10
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10,514