• Documents
  • Authors
  • Tables
  • Log in
  • Sign up
  • MetaCart
  • DMCA
  • Donate

CiteSeerX logo

Advanced Search Include Citations

Tools

Sorted by:
Try your query at:
Semantic Scholar Scholar Academic
Google Bing DBLP
Results 1 - 10 of 20,224
Next 10 →

Power Optimization Issues in Dual Voltage Design

by Anshuman Nayak, Prithviraj Banerjee, Chunhong Chen, Majid Sarrafzadeh - in Proc. of ICDA’00 , 2000
"... In this paper, we look at power optimization issues under dual supply voltage environment, with the goal of optimizing power consumption due to interconnection and gate capacitances. Logic level synthesis is used as a good starting point for power reduction, while subsequent placement stage modifies ..."
Abstract - Cited by 2 (2 self) - Add to MetaCart
In this paper, we look at power optimization issues under dual supply voltage environment, with the goal of optimizing power consumption due to interconnection and gate capacitances. Logic level synthesis is used as a good starting point for power reduction, while subsequent placement stage

Dual Voltage Design for Minimum Energy Using

by Gate Slack, Kyungseok Kim, Vishwani D. Agrawal
"... Abstract—This paper presents a new slack-time based algorithm for dual Vdd design to achieve maximum energy saving. Although a global optimum is sought computation time is kept low. The slack of a gate is defined as the difference between the critical path delay for the circuit and the delay of the ..."
Abstract - Add to MetaCart
. For c880, the energy saving is 22 % for subthreshold voltage operation and 50 % for nominal operation in PTM CMOS 90nm. For c2670 nominal voltage design, time of dual voltage optimization is reduced 44X compared to the MILP method. This new algorithm is beneficial for a large circuits with many large

An Efficient Algorithm for Dual-Voltage Design Without Need for Level Conversion

by Mridula Allani, Vishwani Agrawal , 2012
"... Abstract—We propose a technique to use dual supply voltages in digital designs to reduce energy consumption. New algorithms are proposed for finding and assigning a lower voltage in a dual voltage design. Given a circuit and a supply voltage and an upper bound on the critical path delay, the first a ..."
Abstract - Cited by 3 (3 self) - Add to MetaCart
Abstract—We propose a technique to use dual supply voltages in digital designs to reduce energy consumption. New algorithms are proposed for finding and assigning a lower voltage in a dual voltage design. Given a circuit and a supply voltage and an upper bound on the critical path delay, the first

Energy-Efficient Dual-Voltage Design Using Topological Constraints

by Low Power Electronics, Mridula Allani, Vishwani Agrawal , 2013
"... We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given a ..."
Abstract - Add to MetaCart
We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given

Low-Power CMOS Digital Design

by Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen - JOURNAL OF SOLID-STATE CIRCUITS. VOL 27, NO 4. APRIL 1992 413 , 1992
"... Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the ..."
Abstract - Cited by 580 (20 self) - Add to MetaCart
the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved

A blueprint for introducing disruptive technology into the internet

by Larry Peterson, Tom Anderson, David Culler, Timothy Roscoe , 2002
"... This paper argues that a new class of geographically distributed network services is emerging, and that the most effective way to design, evaluate, and deploy these services is by using an overlay-based testbed. Unlike conventional network testbeds, however, we advocate an approach that supports bot ..."
Abstract - Cited by 593 (43 self) - Add to MetaCart
both researchers that want to develop new services, and clients that want to use them. This dual use, in turn, suggests four design principles that are not widely supported in existing testbeds: services should be able to run continuously and access a slice of the overlay’s resources, control over

Complex wavelets for shift invariant analysis and filtering of signals

by Nick Kingsbury - J. Applied and Computational Harmonic Analysis , 2001
"... This paper describes a form of discrete wavelet transform, which generates complex coefficients by using a dual tree of wavelet filters to obtain their real and imaginary parts. This introduces limited redundancy (2m: 1 for m-dimensional signals) and allows the transform to provide approximate shift ..."
Abstract - Cited by 384 (40 self) - Add to MetaCart
to be shift invariant and describe how to estimate the accuracy of this approximation and design suitable filters to achieve this. We discuss two different variants of the new transform, based on odd/even and quarter-sample shift (Q-shift) filters, respectively. We then describe briefly how the dual tree may

Lockup-free instruction fetch/prefetch cache organization

by David Kroft - In Proceedings of the 8th Annual International Symposium on Computer Architecture , 1981
"... ABSTRACT In the past decade. there has been much literature describing various cache organizatrons that exploit general programming idiosyncrasies to obtain maxrmum hit rate (the probability that a requested datum is now resident in the cache). Little. if any, has been presented to exploit: (1) the ..."
Abstract - Cited by 365 (0 self) - Add to MetaCart
) the inherent dual input nature of the cache and (2) the many-datum reference type central processor instructions. No matter how high the cache hit rate is, a cache miss may impose a penalty on subsequent cache references. This penalty is the necessny of waiting until the missed requested datum is received from

The Dual-Tree Complex Wavelet Transform -- A coherent framework for multiscale signal and image processing

by Ivan W. Selesnick, Richard G. Baraniuk, Nick G. Kingsbury , 2005
"... The dual-tree complex wavelet transform (CWT) is a relatively recent enhancement to the discrete wavelet transform (DWT), with important additional properties: It is nearly shift invariant and directionally selective in two and higher dimensions. It achieves this with a redundancy factor of only 2 ..."
Abstract - Cited by 270 (29 self) - Add to MetaCart
The dual-tree complex wavelet transform (CWT) is a relatively recent enhancement to the discrete wavelet transform (DWT), with important additional properties: It is nearly shift invariant and directionally selective in two and higher dimensions. It achieves this with a redundancy factor of only 2

Improvements to Platt’s SMO Algorithm for SVM Classifier Design

by S. S. Keerthi, S. K. Shevade, C. Bhattacharyya, K. R. K. Murthy , 2001
"... This article points out an important source of inefficiency in Platt’s sequential minimal optimization (SMO) algorithm that is caused by the use of a single threshold value. Using clues from the KKT conditions for the dual problem, two threshold parameters are employed to derive modifications of SMO ..."
Abstract - Cited by 273 (11 self) - Add to MetaCart
This article points out an important source of inefficiency in Platt’s sequential minimal optimization (SMO) algorithm that is caused by the use of a single threshold value. Using clues from the KKT conditions for the dual problem, two threshold parameters are employed to derive modifications
Next 10 →
Results 1 - 10 of 20,224
Powered by: Apache Solr
  • About CiteSeerX
  • Submit and Index Documents
  • Privacy Policy
  • Help
  • Data
  • Source
  • Contact Us

Developed at and hosted by The College of Information Sciences and Technology

© 2007-2019 The Pennsylvania State University