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AND8336 Design Examples of On Board Dual Supply Voltage Logic Translators

by unknown authors
"... Logic translators can be used to connect ICs together that are located on the same PCB and use different supply voltages. Figure 1 lists popular applications that use dual supply voltage translators to interface a microprocessor and ..."
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Logic translators can be used to connect ICs together that are located on the same PCB and use different supply voltages. Figure 1 lists popular applications that use dual supply voltage translators to interface a microprocessor and

Technology Mapping and Clustering for FPGA Architectures with Dual Supply Voltages

by Deming Chen, Jason Cong, Chen Dong, Student Member, Lei He, Senior Member, Fei Li, Chi-chen Peng
"... Abstract—This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. This ..."
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Abstract—This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd

Low-power design methodology and applications utilizing dual supply voltages

by Kimiyoshi Usami, Mutsunori Igarashi - Proceedings of the Asia and South Pacific Design Automation Conference , 2000
"... Abstract- This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview ..."
Abstract - Cited by 22 (0 self) - Add to MetaCart
Abstract- This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview

Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages

by Deming Chen, Jason Cong , 2004
"... In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. We first design a single-Vdd mapping ..."
Abstract - Cited by 20 (5 self) - Add to MetaCart
In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. We first design a single

A shared-well dual-supply-voltage 64-bit ALU

by Yasuhisa Shimazaki, Radu Zlatanovici, Borivoje Nikolić - in IEEE Int. Solid-State Circuits Conf. (ISSCC’03) Dig. Tech. Papers , 2003
"... Abstract—A shared n-well layout technique is developed for the design of dual-supply-voltage logic blocks. It is demonstrated on a design of a 64-bit arithmetic logic unit (ALU) module in domino logic. The second supply voltage is used to lower the power of noncritical paths in the sparse, radix-4 6 ..."
Abstract - Cited by 12 (2 self) - Add to MetaCart
Abstract—A shared n-well layout technique is developed for the design of dual-supply-voltage logic blocks. It is demonstrated on a design of a 64-bit arithmetic logic unit (ALU) module in domino logic. The second supply voltage is used to lower the power of noncritical paths in the sparse, radix-4

On Gate Level Power Optimization Using Dual-Supply Voltages

by Chunhong Chen, Ankur Srivastava, Student Member, Majid Sarrafzadeh - IEEE Trans. on VLSI Systems , 2001
"... In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed ..."
Abstract - Cited by 37 (3 self) - Add to MetaCart
different power consumption, we propose a fast heuristic approach to predict the optimum dual-supply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a

MICROPROCESSORS LEAKAGE POWER REDUCTION USING DUAL SUPPLY VOLTAGE SCALING

by Diary R. Sulaiman
"... Power efficient design is one of the most important goals for microprocessors, especially in the design of portable, notebook, and handheld computers. In the new high performance designs the static or leakage power is expected to increase because of the exponential increase in leakage currents with ..."
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and methodologies for power dissipation reduction. This paper presents a hardware design and implementation for microprocessors leakage power reduction using dual supply voltage scaling, and it can be considered as an effective mechanism for reducing processors power and energy while preserving performance

Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages

by unknown authors
"... Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption due to the quadratic relation of supply voltage to power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespre ..."
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Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption due to the quadratic relation of supply voltage to power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing

Provably good algorithm for low power consumption with dual supply voltages

by Chunhong Chen , Majid Sarrafzadeh - IEEE/ACM International Conference on Computer Aided Design , 1999
"... Abstract Dual-voltage approach emerges as an effective and practical ..."
Abstract - Cited by 14 (4 self) - Add to MetaCart
Abstract Dual-voltage approach emerges as an effective and practical

Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages

by Vijay Sundararajan, Keshab K. Parhi - in Proceedings of the Design Automation Conference , 1999
"... Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply voltage for gates off the critical path it is possible to dramatically reduce power consumption in CMOS VLSI circuits wi ..."
Abstract - Cited by 15 (1 self) - Add to MetaCart
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply voltage for gates off the critical path it is possible to dramatically reduce power consumption in CMOS VLSI circuits
Results 1 - 10 of 8,757