Results 1 - 10 of 3,094

Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing

by Edward Ashford Lee, David G. Messerschmitt - IEEE TRANSACTIONS ON COMPUTERS , 1987
"... Large grain data flow (LGDF) programming is natural and convenient for describing digital signal processing (DSP) systems, but its runtime overhead is costly in real time or cost-sensitive applications. In some situations, designers are not willing to squander computing resources for the sake of pro ..."
Abstract - Cited by 598 (37 self) - Add to MetaCart
Large grain data flow (LGDF) programming is natural and convenient for describing digital signal processing (DSP) systems, but its runtime overhead is costly in real time or cost-sensitive applications. In some situations, designers are not willing to squander computing resources for the sake

Synchronous data flow

by Edward A. Lee, et al. , 1987
"... Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case ..."
Abstract - Cited by 622 (45 self) - Add to MetaCart
Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case

An efficient VLIW DSP architecture for baseband processing

by Tay-jyi Lin, Chin-chi Chang, Chen-chia Lee, Chein-wei Jen - Proceedings of the 21st International Conference on Computer Design, IEEE Computer Society Press: Los Alamitos, CA , 2003
"... The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for high-performance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing rate ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for high-performance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing

Dataflow Process Networks

by Edward A. Lee, Thomas Parks - Proceedings of the IEEE , 1995
"... We review a model of computation used in industrial practice in signal processing software environments and experimentally in other contexts. We give this model the name "dataflow process networks," and study its formal properties as well as its utility as a basis for programming language ..."
Abstract - Cited by 325 (32 self) - Add to MetaCart
We review a model of computation used in industrial practice in signal processing software environments and experimentally in other contexts. We give this model the name "dataflow process networks," and study its formal properties as well as its utility as a basis for programming language

USING C-TO-HARDWARE ACCELERATION IN FPGAS FOR WAVEFORM BASEBAND PROCESSING

by unknown authors
"... Software-defined radio (SDR) architectures typically include general-purpose CPUs (GPPs), digital signal processing (DSP) ASSPs and FPGAs that process different waveforms, functions, and algorithms. GPPs typically handle network protocol processing and management functions. Historically, DSPs handle ..."
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handled transceiver baseband processing and encoding, while FPGAs provided highperformance IF up/down conversion and preconditioning functions. Now FPGAs, when used with embedded softcore processors, have absorbed the DSP baseband processing and some GPP functionality as well, providing a smaller, lower

A Programmable DSP core for Baseband Processing, submitted to 3rd

by Eric Tell , Anders Nilsson , Dake Liu - International IEEE North East Workshop Circuits and Systems , 2005
"... Abstract-A programmable baseband processor architecture is presented. The architecture is based on a specialized DSP processor core and a number accelerators connected via a configurable network. The focus of this paper is the DSP core itself. A novel type of instructions operating on vectors of co ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
Abstract-A programmable baseband processor architecture is presented. The architecture is based on a specialized DSP processor core and a number accelerators connected via a configurable network. The focus of this paper is the DSP core itself. A novel type of instructions operating on vectors

SPIRAL: Code Generation for DSP Transforms

by Markus Püschel, José M. F. Moura, Jeremy Johnson, David Padua, Manuela Veloso, Bryan W. Singer, Jianxin Xiong, Franz Franchetti, Aca Gačić, Yevgen Voronenko, Kang Chen, Robert W. Johnson, Nicholas Rizzolo - PROCEEDINGS OF THE IEEE SPECIAL ISSUE ON PROGRAM GENERATION, OPTIMIZATION, AND ADAPTATION
"... Fast changing, increasingly complex, and diverse computing platforms pose central problems in scientific computing: How to achieve, with reasonable effort, portable optimal performance? We present SPIRAL that considers this problem for the performance-critical domain of linear digital signal proces ..."
Abstract - Cited by 222 (41 self) - Add to MetaCart
processing (DSP) transforms. For a specified transform, SPIRAL automatically generates high performance code that is tuned to the given platform. SPIRAL formulates the tuning as an optimization problem, and exploits the domain-specific mathematical structure of transform algorithms to implement a feedback

Implementation of Programmable Baseband Processors

by Dake Liu, Eric Tell, Anders Nilsson
"... Abstract – Implementation of programmable baseband DSP processors for digital radio communications is discussed in this paper. An implementation example based on IEEE802.11a/b/g WLAN is given. Key words: Baseband signal processing, ASIP. 1. ..."
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Abstract – Implementation of programmable baseband DSP processors for digital radio communications is discussed in this paper. An implementation example based on IEEE802.11a/b/g WLAN is given. Key words: Baseband signal processing, ASIP. 1.

A 1-V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital . . .

by Hui Zhang, Ana Prabhu, Varghese George, Marlene Wan, Martin Benes, Arthur Abnous, Jan M. Rabaey - IEEE JOURNAL OF SOLID STATE CIRCUITS , 2000
"... A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm 6.7 mm prototype processor, targeted for voice compression, is implemented in ..."
Abstract - Cited by 16 (0 self) - Add to MetaCart
A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm 6.7 mm prototype processor, targeted for voice compression, is implemented

1000BASE-T Gigabit Ethernet Baseband DSP IC Design

by Hsiu-ping Lin, Nancy F. Chen, Jyh-ting Lai, An-yeu Wu
"... Abstract- The design of Gigabit Ethernet baseband DSP IC is based on IEEE standard 802.3ab and focuses on signal processing in 1000BASE-T PHY layer. To achieve the target bit-error rate (BER) of less than 10-10, the receiver must conquer channel impairments including Inter-Symbol ..."
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Abstract- The design of Gigabit Ethernet baseband DSP IC is based on IEEE standard 802.3ab and focuses on signal processing in 1000BASE-T PHY layer. To achieve the target bit-error rate (BER) of less than 10-10, the receiver must conquer channel impairments including Inter-Symbol
Results 1 - 10 of 3,094