Results 1 - 10 of 564

Subthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance

by Muralidharan Venkatasubramanian, Vishwani D. Agrawal
"... Abstract — Evolving nanometer CMOS technologies provide low power, high performance and higher levels of integration but suffer from increased subthreshold leakage and excessive process variation. The present work examines the 45nm bulk and high-k technologies. We evaluate the performance of a 32-bi ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
compared to bulk. The energy per cycle versus supply voltage is a U-shaped curve whose bottom, the minimum energy point, provides a stable equilibrium against speed and energy deviations due to process related parametric variations for different technologies. These deviations can be expected to be lower

Dynamic voltage and frequency scaling circuits with two supply voltages

by Wayne H. Cheng, Bevan M. Baas - in IEEE Intl. Symposium on Circuits and Systems (ISCAS , 2008
"... Abstract — This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power dissipation. Each processor can run on either a high voltage or low voltage power supply, or disconnect from both. Switching ..."
Abstract - Cited by 8 (3 self) - Add to MetaCart
Abstract — This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power dissipation. Each processor can run on either a high voltage or low voltage power supply, or disconnect from both

EFFECT OF SOURCE VOLTAGE SUBHARMONICS ON A RAPID CYCLING SYNCHROTRON POWER SUPPLY

by unknown authors
"... In a 50 Hz rapid cycling power supply, the resonant ac current of the synchrotron magnet is modulated by the subharmonics of the source voltage rectified in 12 pulses with SCR. The modulation is found to be caused by the fluctuation of the pulsed power that is transferred to the magnet circuit via a ..."
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In a 50 Hz rapid cycling power supply, the resonant ac current of the synchrotron magnet is modulated by the subharmonics of the source voltage rectified in 12 pulses with SCR. The modulation is found to be caused by the fluctuation of the pulsed power that is transferred to the magnet circuit via

Field Programmability of Supply Voltages for FPGA Power Reduction

by Fei Li, Yan Lin, Lei He , 2007
"... Power reduction is of growing importance for field-programmable gate arrays (FPGAs). In this paper, we apply programmable supply voltage (Vdd) to reduce FPGA power. We first design FPGA logic fabrics using dual-Vdd levels and show that field-programmable power supply is required to obtain a satisfa ..."
Abstract - Cited by 4 (0 self) - Add to MetaCart
Power reduction is of growing importance for field-programmable gate arrays (FPGAs). In this paper, we apply programmable supply voltage (Vdd) to reduce FPGA power. We first design FPGA logic fabrics using dual-Vdd levels and show that field-programmable power supply is required to obtain a

Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance

by Min Chen, Student Member, Gabriel A. Rincón-mora, Senior Member - IEEE Transactions on Energy Conversion , 2006
"... Abstract—Low power dissipation and maximum battery runtime are crucial in portable electronics. With accurate and efficient circuit and battery models in hand, circuit designers can predict and optimize battery runtime and circuit performance. In this paper, an accurate, intuitive, and comprehensive ..."
Abstract - Cited by 116 (2 self) - Add to MetaCart
model neglecting the effects of self-discharge, cycle number, and temperature, which are nonconsequential in low-power Li-ion-supplied applications, is validated with experimental data on NiMH and polymer Li-ion batteries. Less than 0.4 % runtime error and 30-mV maximum error voltage show

Reducing Cache Energy Through Dual Voltage Supply

by Vasily G. Moshnyaga
"... Abstract- Due to a large capacitance and enor-mous access rate, caches dissipate about a third of the total energy consumed by today’s processors. In this paper we present a new architectural tech-nique to reduce energy consumption in caches. Un-like previous approaches, which have focused on low-er ..."
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-ering cache capacitance and the number of accesses, our method exploits a new freedom in cache design, namely the voltage per access. Since in modern caches, the loading capacitance operated on cache-hit is much less than the capacitance operated on cache-miss, the given clock cycle time is inefficiently exp

Voltage FB

by Power Factor Controller, Case K
"... The MC33368 is an active power factor controller that functions as a boost preconverter in off-line power supply applications. MC33368 is optimized for low power, high density power supplies requiring a minimum board area, reduced component count and low power dissipation. The narrow body SOIC packa ..."
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line voltage a zero current detector to ensure critical conduction operation, a transconductance error amplifier, a current sensing comparator, a 5.0 V reference, an undervoltage lockout (UVLO) circuit which monitors the VCC supply voltage and a CMOS driver for driving MOSFETs. The MC33368 also

Virtuoso Multiple Supply Multiple Voltage (MSMV) Support

by Nidhi Malik, Silicon Valley
"... There are innumerable issues that designers face while working with designs that include multiple power supplies in a single IC (most cases for SoCs today). As the design progresses from a conceptual stage to a more concrete implementation stage, various levels of representations for the design emer ..."
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There are innumerable issues that designers face while working with designs that include multiple power supplies in a single IC (most cases for SoCs today). As the design progresses from a conceptual stage to a more concrete implementation stage, various levels of representations for the design

Dynamic Task-Level Voltage Scheduling Optimizations∗

by Jeffrey A. Barnett
"... Energy versus delay tradeoffs are explored for systems that must manage energy expenditure as well as computation deadlines. The focus is execution of a single process on a single processor. Two probabilistic process models are considered along with a family of power dissipation models. The first pr ..."
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and that execution time for a cycle is proportional to v−n, where v is supply voltage. The energy versus delay tradeoff is implemented using dynamic voltage and clock adjustments. The problems solved include 1) minimize expected execution time given a hard energy budget and 2) minimize expected energy expenditure

True Minimum Energy Design Using Dual Below-Threshold Supply Voltages

by Kyungseok Kim, Vishwani D. Agrawal - INTERNATIONAL CONFERENCE ON VLSI DESIGN , 2011
"... This paper investigates subthreshold voltage operation of digital circuits. The minimum energy per cycle operating point with a single voltage for this mode is known. We further lower the energy per cycle below that point by using dual subthreshold supplies. We call this the true minimum. Special co ..."
Abstract - Cited by 6 (5 self) - Add to MetaCart
This paper investigates subthreshold voltage operation of digital circuits. The minimum energy per cycle operating point with a single voltage for this mode is known. We further lower the energy per cycle below that point by using dual subthreshold supplies. We call this the true minimum. Special
Results 1 - 10 of 564