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386
System-level design: Orthogonalization of concerns and platform-based design
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2000
"... System-level design issues become critical as implementation technology evolves toward increasingly complex integrated circuits and the time-to-market pressure continues relentlessly. To cope with these issues, new methodologies that emphasize re-use at all levels of abstraction are a “must”, and th ..."
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Cited by 272 (10 self)
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”, and this is a major focus of our work in the Gigascale Silicon Research Center. We present some important concepts for system design that are likely to provide at least some of the gains in productivity postulated above. In particular, we focus on a method that separates parts of the design process and makes
Buried Cobalt Silicide Layers in Silicon Created by Wafer Bonding
"... A buried conductive layer in silicon has been created using wafer bonding technique, with a cobalt interracial layer. Co-coated silicon wafers were brought into contact with either similar or uncoated wafers at room temperature. CoSt2 was then formed through as01id-phase r action, during an anneal a ..."
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at 700 to 900 ~ A 700 A buried CoSi2-1ayer, with a resistivity of approximately 21 ~ cm, was achieved. Good adhesion, as measured by tensile strength testing, between the wafers was achieved. Transmission electron microscopic investigations (Co-coated wafer bonded to bare silicon) showed
Silicon chemical vapor deposition process using a half-inch silicon wafer for Minimal Manufacturing System
, 2013
"... Abstract A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed ..."
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Abstract A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed
Technologies for 3D Wafer Level Heterogeneous Integration
, 2008
"... Abstract-3D integration is a fast growing field that encompasses different types of technologies. The paper addresses one of the most promising technology which uses Through Silicon Vias (TSV) for interconnecting stacked devices on wafer level to perform high density interconnects with a good electr ..."
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with redistribution layers and TSV. I. DRIVERS FOR 3D SYSTEM INTEGRATION Since several years packaging is driven by System in Package (SiP) solutions to meet the requirements of improved performance, miniaturization and cost reduction. This leads to a number of technologies where 3D system integration is one
New Manufacturing Concepts for Ultra-Thin Silicon and Gallium Arsenide Substrates
"... The paper reports on new manufacturing concepts for handling and processing of thin semiconductor substrates. Technologies which were formerly demonstrated for silicon wafers were recently transferred to GaAs substrates and are presented in this paper. As a result of the development work the feasibi ..."
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Cited by 2 (1 self)
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The paper reports on new manufacturing concepts for handling and processing of thin semiconductor substrates. Technologies which were formerly demonstrated for silicon wafers were recently transferred to GaAs substrates and are presented in this paper. As a result of the development work
UNCERTAINTY IN THE TEMPERATURE OF SILICON WAFERS MEASURED BY RADIATION THERMOMETRY BASED UPON A POLARIZATION TECHNIQUE
, 2009
"... Abstract − The emissivity behaviour of a silicon wafer under various conditions was theoretically and experimentally investigated. As a result, the quantitative relationship between the ratio of p-polarized radiance to s-polarized one, and polarized emissivities was obtained irrespective of the emis ..."
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Abstract − The emissivity behaviour of a silicon wafer under various conditions was theoretically and experimentally investigated. As a result, the quantitative relationship between the ratio of p-polarized radiance to s-polarized one, and polarized emissivities was obtained irrespective
Development of Low Dark Current SiGe Near-Infrared PIN Photodetectors on 300 mm Silicon Wafers
"... Abstract SiGe offers a low-cost alternative to conventional infrared sensor material systems such as InGaAs, InSb, and HgCdTe for developing near-infrared (NIR) photodetector devices that do not require cooling and can operate with relatively low dark current. As a result of the significant differe ..."
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Abstract SiGe offers a low-cost alternative to conventional infrared sensor material systems such as InGaAs, InSb, and HgCdTe for developing near-infrared (NIR) photodetector devices that do not require cooling and can operate with relatively low dark current. As a result of the significant
The Wafer Breakages Reduction Using Kaizen Approach
"... Abstract The solar industries not only suffers from shortage of silicon but also price hike as a consequence in other hand the competition are high they need to reduce the selling price in order to be competitive. With current cost of silicon wafer that representing 60% of the solar cell cost rathe ..."
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rather than getting cheaper solar cell from the manufacturer, there is a new growing trend to reduce the silicon wafer thickness from 200micron to 180 micron and future to 150 micron later and leading to new technical challenges related to manufacturing process. Specifically on wafer breakage during
Coupled Simulation to Determine Across Wafer Variations for Electrical and Reliability Parameters of Through-Silicon Vias
"... Three-dimensional (3D) integration of integrated circuits is a key challenge for the future evolution of semiconductor systems. Through silicon vias (TSV) are an integral component for interconnecting stacked circuits. For the fabrication of TSVs, a sequence of processing steps is required, includi ..."
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Three-dimensional (3D) integration of integrated circuits is a key challenge for the future evolution of semiconductor systems. Through silicon vias (TSV) are an integral component for interconnecting stacked circuits. For the fabrication of TSVs, a sequence of processing steps is required
Exploring the Silicon Design Limits of Thin Wafer IGBT Technology: The Controlled Punch Through (CPT) IGBT
"... Abstract- The paper introduces a new Controlled Punch Through (CPT) IGBT buffer for next generation devices, which utilise thin wafers technology. The new concept is based on very shallow buffers with optimized doping profiles enabling minimum silicon design thicknesses close to the theoretical limi ..."
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Cited by 1 (1 self)
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Abstract- The paper introduces a new Controlled Punch Through (CPT) IGBT buffer for next generation devices, which utilise thin wafers technology. The new concept is based on very shallow buffers with optimized doping profiles enabling minimum silicon design thicknesses close to the theoretical
Results 1 - 10
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386