Searching for authors named Shantanu Dutt – sorted by Relevance.
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Research Accomplishments
- Research Accomplishments Shantanu Dutt Department of Electrical and Computer Engineering Univ
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New Faster Kernighan-Lin-Type Graph-Partitioning Algorithms
- New Faster Kernighan-Lin-Type Graph-Partitioning Algorithms Shantanu Dutt Department
- Cited by 16 (3 self) – Add To MetaCart
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Scalable Duplicate Pruning Strategies for Parallel A* Graph Search
- and Shantanu Dutt Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455
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New Anticipatory Load Balancing Strategies for Parallel A* Algorithms
- * Algorithms Nihar R. Mahapatra and Shantanu Dutt fmahapatra, duttg@(email omitted); Department of Electrical
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Effective Partition-Driven Placement with Simultaneous Level Processing and Global Net Views
- Zhong and Shantanu Dutt Dept. of EECS, University of Illinois-Chicago Abstract : In this paper we take a
- Cited by 7 (0 self) – Add To MetaCart
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Mixed PLB and Interconnect BIST for FPGAs without Fault-Free Assumptions
- and Shantanu Dutt Department of Electrical and Computer Engineering, Univ. of Illinois at Chicago ¡ vsuthar
- Cited by 1 (0 self) – Add To MetaCart
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Partitioning Using Second-Order Information and Stochastic-Gain Functions
- Partitioning Using Second-Order Information and Stochastic-Gain Functions Shantanu Dutt 1
- Cited by 5 (0 self) – Add To MetaCart
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on Security in Reconfigurable Systems Design, 2008 Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures
- -Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures SHANTANU DUTT and LI LI Dept
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Algorithms for Simultaneous Consideration of Multiple Physical Synthesis Transforms for Timing Closure ∗
- Consideration of Multiple Physical Synthesis Transforms for Timing Closure ∗ Huan Ren and Shantanu Dutt Dept
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A Network-Flow Based Cell Sizing Algorithm
- A Network-Flow Based Cell Sizing Algorithm Huan Ren and Shantanu Dutt Dept. of ECE, University
- Cited by 1 (1 self) – Add To MetaCart

