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Searching for authors named Shantanu Dutt – sorted by Relevance.

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28 documents found, showing 1 through 10. Next 10 →

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Research Accomplishments
by Shantanu Dutt
…Research Accomplishments Shantanu Dutt Department of Electrical and Computer Engineering Univ…
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New Faster Kernighan-Lin-Type Graph-Partitioning Algorithms
by Shantanu Dutt — 1993 — In Proc. IEEE Intl. Conf. Computer-Aided Design
…New Faster Kernighan-Lin-Type Graph-Partitioning Algorithms Shantanu Dutt Department…
Cited by 16 (3 self) – Add To MetaCart

Scalable Duplicate Pruning Strategies for Parallel A* Graph Search
by Nihar Mahapatra Shantanu, Shantanu Dutt — 1993 — In Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing
… and Shantanu Dutt Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455…
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New Anticipatory Load Balancing Strategies for Parallel A* Algorithms
by Nihar Mahapatra Shantanu, Shantanu Dutt — 1995 — In Proceedings of the DIMACS Series on Discrete Mathematics and Theoretical Computer Science
…* Algorithms Nihar R. Mahapatra and Shantanu Dutt fmahapatra, duttg@(email omitted); Department of Electrical…
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Effective Partition-Driven Placement with Simultaneous Level Processing and Global Net Views
by Ke Zhong, Shantanu Dutt — 2000 — In Proc. Int. Conf. on Computer Aided Design
… Zhong and Shantanu Dutt Dept. of EECS, University of Illinois-Chicago Abstract : In this paper we take a…
Cited by 7 (0 self) – Add To MetaCart

Mixed PLB and Interconnect BIST for FPGAs without Fault-Free Assumptions
by Vishal Suthar, Shantanu Dutt — in Proceedings of VLSI Test Symposium (VTS2006), 2006
… and Shantanu Dutt Department of Electrical and Computer Engineering, Univ. of Illinois at Chicago ¡ vsuthar…
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Partitioning Using Second-Order Information and Stochastic-Gain Functions
by Shantanu Dutt, Halim Theny — 1998 — Proc. IEEE/ACM International Symposium on Physical Design
…Partitioning Using Second-Order Information and Stochastic-Gain Functions Shantanu Dutt 1…
Cited by 5 (0 self) – Add To MetaCart

on Security in Reconfigurable Systems Design, 2008 Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures
by Shantanu Dutt, Li Li
…-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures SHANTANU DUTT and LI LI Dept…
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Algorithms for Simultaneous Consideration of Multiple Physical Synthesis Transforms for Timing Closure ∗
by Huan Ren, Shantanu Dutt
… Consideration of Multiple Physical Synthesis Transforms for Timing Closure ∗ Huan Ren and Shantanu Dutt Dept…
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A Network-Flow Based Cell Sizing Algorithm
by Huan Ren, Shantanu Dutt — 2008 — The International Workshop on Logic Synthesis
…A Network-Flow Based Cell Sizing Algorithm Huan Ren and Shantanu Dutt Dept. of ECE, University…
Cited by 1 (1 self) – Add To MetaCart

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