Abstract—Soft on-FGPA interconnection networks are gain-ing increasing importance since they simplify the integration of heterogeneous components and offer, at the same time, a modular solution to the complex system-wide communication issues. The switches are the basic building blocks

Abstract—On-chip interconnection networks simplify the inte-gration of complex system-on-chips. The switches are the basic building blocks of such networks and their design critically affects the performance of the whole system. The transfer of data between the inputs and the outputs of the switch

second of computation. Building balanced computing systems in the multicore era with hundreds of processing cores per die is challenging because of the pin limitations and poor scalability of bandwidth and memory capacity with off-chip electrical interconnects between the CPU and memory subsystem. We

This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class of interconnect architectures. It shows that the design choices for the interconnect have significant effect on the rest

..................................................................... ....... i Acknowledgements ............................................................... ii 1. Introduction .................................................................... 1 2. Quality of Service Terminology, Principles and Concepts ................. 17 2.1 Terminology.......................................................... .......................17 2.2 Qos Principles........................................................... ...................18 2.2.1 Integration Principle .................................................................19 2.2.2 Separation Principle .................................................................19 2.2.3 Transparency Principle............................................................ ..19 2.2.4 Asynchronous Resource Management Principle .................................20 2.2.5 Performance Principle............................................................ ...20 2.3 QoS S...

as the overall MP-SoC interconnect architecture, thereby offering an attractive alternative for SoC interconnect that does not suffer from the non-scalability aspect of the buses in regards to the clock cycle.

This paper describes the interconnection network used in the Cray T3E multiprocessor. The network is a bidirectional 3D torus with fully adaptive routing, optimized virtual channel assignments, integrated barrier synchronization support and considerable fault tolerance. The routers are built

Abstract−Application-specific or embedded systems with less than 16 processing cores are too small to use some kind of network on chip (NoC) for interconnection. On the other hand, a crossbar and related circuitry (arbiters, memory elements) are too expensive in terms of chip area. As only few pair

Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection networks for clustered microarchitectures. This new class

In this paper, we propose a new congestion management strategy for lossless multistage interconnection networks that scales as network size and/or link bandwidth increase. Instead of eliminating congestion, our strategy avoids performance degradation beyond the saturation point by eliminating