"... In PAGE 7: ...able 1-1: ENACTS Participants by Role and Skills..............................................................2 Table2 -1: Level for RAID technology.... In PAGE 7: ...able 2-1: Level for RAID technology................................................................................12 Table2 -2: Secondary storage technology.... In PAGE 7: ...able 2-2: Secondary storage technology. .........................................................................13 Table2 -3: Tertiary storage roadmap .... In PAGE 7: ...able 2-3: Tertiary storage roadmap ...................................................................................15 Table2 -4: interconnection protocols comparaison.... In PAGE 7: ...able 2-4: interconnection protocols comparaison..............................................................16 Table2 -5: SAN vs.... In PAGE 7: ...able 2-5: SAN vs. NAS ........................................................................................................17 Table2 -6: Sample of RasQL.... In PAGE 19: ... The RAID array is the configuration used to assemble disks, in order to obtain performance and reliability. The basic characteristics of different configurations are found in Table2 -1. RAID A disk array in which part of the physical storage capacity is used to store redundant information about user data stored on the remainder of the storage capacity.... In PAGE 19: ... Level 6 As RAID 5, but with additional independently computed check data. Table2 -1: Level for RAID technology. ... In PAGE 20: ... Table2 -2: Secondary storage technology. In contrast to secondary storage, assembling tertiary systems from commodity components is much more difficult, although individual tertiary drives may be as fast as or faster than disk.... In PAGE 22: ...enacts.org October 2003 15 Tertiary Storage Technology Timeline 1999 2001 2004 Tape Transfer Rate 10-20 MB/sec 20-40 MB/sec 40-80 MB/sec (may be higher with breakthrough technology) Mount and Positioning Latency 50-100 sec 50-100 sec 50-100 sec Single Removable Volume Capacity 50-100 GB 250-500 GB 1 TB Active Drives per RAIT 8 8 8 Number of RAITs (40% of SAN bandwidth) 8 32 125 Total Parallel Drives 64 256 1000 Table2 -3: Tertiary storage roadmap 2.3 Interconnection technology From the user apos;s point of view, data can be local, directly available to the user; or remote - accessible through a network.... In PAGE 22: ... The latter, as standard command protocol is carried also over Fibre Channel connections and over IP connections (called iSCSI). A comparison between these protocols is briefly described in Table2 -4. ... In PAGE 23: ...3, 66.6, 100 SCSI 1 8-bit 5 Fast Wide SCSI 16-bit 20 Ultra SCSI 8-bit 20 Wide Ultra SCSI 16-bit 40 Ultra2 SCSI 8-bit 40 Wide Ultra2 SCSI 16-bit 80 Ultra3 SCSI (Ultra160 SCSI) 16-bit 160 Ultra320 SCSI 16-bit 320 Table2 -4: interconnection protocols comparaison The universal Fiber Channel (FC) protocol, based on fibre optics, has reached a wide diffusion due to its multi protocol interface support. This protocol also supports reliable topologies such as FC-AL (ring).... In PAGE 24: ... All NAS and SAN configurations use available, standard technologies: NAS takes RAID disks and connects them to the network using Ethernet or other LAN topologies, while SAN implementations will provide a separate data network for disks and tape devices using the Fibre Channel equivalents of hubs, switches and cabling. Table2 -5 highlights some of the key characteristics of both SAN and NAS. SAN NAS Protocol Fibre Channel (Fibre Channel-to- SCSI) TCP/IP Application Mission-critical transactions.... In PAGE 24: ...apacity. No distance limitations. Easy deployment and maintenance. Table2 -5: SAN vs. NAS SAN can provide high-bandwidth block storage access over a long distance via extended Fibre Channel links.... In PAGE 36: ...enacts.org October 2003 29 MARRAY Select marray n in [0:255] values condense + over x in sdom(v) using v[x]=n from VolumetricImages as v For each 3-D image its histogram COND Select condense + over x in sdom(w) using w[x] gt; t from Warehouse as w For each datacube in the warehouse, count all cells exceeding threshold value t Table2 -6: Sample of RasQL 2.6.... ..."

"... In PAGE 4: ... We conclude with some data on embedded CPUs supporting our claim regarding the special relation between inlining and embedded systems. Table1 lists the leading high-end embedded processors and the number of entries in their branch direction (Branch History Table) and branch target predictors (Branch Target Buffer), and the number of entries in their return stacks. Many have little or no support for branch target predictions, in particular for return address predictions.... ..."

"... In PAGE 9: ...throttling (App) on Intel Xeon system. Method Number Number Time (s) of of of Total dSdC InvD W Throttling Writers Readers TIO+LBSTIO TIO LBSTIO TIO LBSTIO TIO LBSTIO UT 4 4 243 12 9 83 3 77 1 System 1 1 213 67 12 72 5 63 5 App 1 1 189 18 9 48 10 42 10 Table1 0: I/O and total execution times of unthrottled case (UT), system software throttling (System), and the best-case appli- cation throttling (App) on IBM p690. Method Number Number Time (s) of of of Total dSdC InvD W Throttling Writers Readers TIO+LBSTIO TIO LBSTIO TIO LBSTIO TIO LBSTIO UT 16 16 355 56 3 157 6 144 5 System 1 1 339 25 18 97 30 82 20 App 1 1 311 31 37 59 46 51 43 (a) No throttling (b) Throttled by application (c) Throttled by system software (d) Throttled by system software Figure 4: Impact of throttling on individual task execution times; (c) and (d) show the varying nature of task times across two executions.... ..."

"... In PAGE 13: ...Olaf Schenk et al. 3 Comparing Algorithms and Machines for Complete Semiconductor Device Simulations For our comparison in Table4 , we used ve typical semiconductor device simula- tion cases: one 2-D transient simulation with a hydrodynamic model and 14 apos;662 vertices (87 apos;732 unknowns), and four 3-D quasistationary device simulations, with 10 apos;870, 12 apos;699, 26 apos;855, and 105 apos;237 vertices (32 apos;610, 38 apos;097, 80 apos;565, and 315 apos;711 unknowns), respectively. All grids are highly irregular and the linear systems are very sparse.... In PAGE 13: ... This nested dissection ll-reducing ordering is substantially better than the multiple minimum degree algorithm for large prob- lem sizes (up to a factor up 5 in oating point operations for larger 3-D grids). Table4 clearly re ects the performance di erence due to algorithmic improve- ments. On the other side, preconditioned sparse iterative methods play an important role in the area of semiconductor device and process simulation problems.... In PAGE 13: ...or non trivial examples is in the range of 0.01 to 0.001 times that found for a direct method. Furthermore, looking at the quasistationary 3-D simulation with 105 apos;237 vertices in Table4... ..."

"... In PAGE 8: ... Especially Figure 7 demonstrates the in uence of algorithmic and hardware properties. 4 Comparing Algorithms and Machines for complete Semiconductor Device Simulations For our comparison in Table3 , we used ve typical semiconductor device simula- tion cases: one 2-D transient simulation with a hydrodynamic model and 14 apos;662 vertices (87 apos;732 unknowns), and four 3-D quasistationary device simulations, with 10 apos;870, 12 apos;699, 26 apos;855, and 105 apos;237 vertices (32 apos;610, 38 apos;097, 80 apos;565, and 315 apos;711 unknowns), respectively. All grids are highly irregular and the linear systems are very sparse.... In PAGE 9: ... This nested dissection ll-reducing ordering is substantially bet- ter than the multiple minimum degree algorithm for large problem sizes (up to a factor up 5 in oating point operations for larger 3-D grids). Table3 clearly re ects the performance di erence due to algorithmic improvements. Table 3.... In PAGE 10: ...or non trivial examples is in the range of 0.01 to 0.001 times that found for a direct method. Furthermore, looking at the quasistationary 3-D simulation with 105 apos;237 vertices in Table3 we see that the iterative solver failed during the simulation. The main memory requirement of DESSIS?ISE with the parallel direct solver was about 4 Gbytes on the SGI Origin 2000 for the largest example with 105 apos;237 vertices.... ..."

"... In PAGE 3: ...ous tag bits, respectively, that are available for other use, potentially as branch prediction bits. Table1 lists the IBM ESA/370 branches, their fre- quencies relative to all instructions in a TSO-XA oper- ating system representative workload trace, their fre- quencies relative to branch instructions only, their fre- quencies of taken and not taken outcomes, and their length in halfwords. From the de nition of the instruc- tions and their lengths, the branches may be further subdivided as follows: 1.... ..."

"... In PAGE 3: ... 4.1 Camera Performance Table1 presents the performance characteristics of the high-end camera that we currently use to track objects in close-up. 4.... ..."