Searching for authors named Luis Entrena – sorted by Relevance.
6 documents found, showing 1 through 6.
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Timing Optimization by an Improved Redundancy Addition and Removal Technique
- …Timing Optimization by an Improved Redundancy Addition and Removal Technique Luis A. Entrena…
- Cited by 4 (3 self) – Add To MetaCart
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Automatic generation of fault tolerant VHDL designs
- …Automatic Generation of Fault Tolerant VHDL Designs in RTL Luis Entrena, Celia López, Emilio Olías…
- Cited by 2 (0 self) – Add To MetaCart
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Olías, “Automatic Insertion of Fault-Tolerant Structures at the RT
- …Automatic Insertion of Fault-Tolerant Structures at the RT Level Luis Entrena, Celia López, Emilio…
- Cited by 3 (2 self) – Add To MetaCart
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Integrating symbolic techniques in ATPG-based sequential logic optimization
- …, Luis Entrena, José A. Espejo, *Silvia Chiusano, *Fulvio Corno Universidad Carlos III de Madrid. Dpto…
- Cited by 1 (0 self) – Add To MetaCart
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An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
- … BERROJO * , Fulvio CORNO ** , Luis ENTRENA *** , Isabel GONZÁLEZ * , Celia LOPEZ *** , Matteo SONZA REORDA…
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Analysis of the Equivalences and Dominances of Transient Faults at the RT Level
- …, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza, Giovanni Squillero Alcatel…
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Showing 1 through 6.
