is a composition of a Reconfigurable Control Unit (RCU) and a Reconfigurable Function Unit (RFU). Each unit consists of hardwired (fixed) and programmable components. The paper considers and analyses methods, which can be used for logic synthesis and optimisation of RCP based on such decomposition.

technological and computer experiments with application of these methods produce promising results, this kind of logic synthesis will probably dominate the development of digital circuits for FPGA structures. Many examples confirming effectiveness of decomposition method in technology mapping in digital

The paper introduces a new technique for on-line checking of FPGA based Control Units (CUs). This technique is based on the architecture comprising two portions: a self-checking CU and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination

. Specifically, multi-clock domain behavior makes it difficult to ensure that reconvergent multi-FPGA paths that are sourced and sampled by multiple asynchronous design clocks can be evaluated accurately. In this paper, we describe scheduling and synthesis techniques that address the reconvergent fanout problem

Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, greatly simplify the design of large circuits

This paper describes the design and implementation of mobile robot subsumption architecture in which the computing elements of control are based on programmable FPGA devices. This paper also shows the marriage of two concepts, subsumption architecture and FPGA design. To demonstrate

of this design. The design maintains a restricted instruction set, and consists of four major components: 1) the hazard free speed optimized Control unit, 2) a two stage pipelined data path, 3) a single cycle multiply and accumulator (MAC) and 4) a system memory. Harvard architecture is used to improve

date from these units. The GCHU is the joystick control providing inputs to the CU based on control movement and firing operations initiated by the operator. The original test requirements for the DU called for a manual test using a custom DU interface test box. The manual-only design made integration

are efficient for layout flexible ASICs but are clearly not adequate for reconfigurable devices with pre-defined architectures because of control overhead and complex routing requirements. The compilation flow takes advantage of a specialized library of circuit-generators and only resorts to logic synthesis

controlled-NOTs). They are based on an analogue of the Shannon decomposition of Boolean functions and a new circuit block, quantum multiplexor, that generalizes several known constructions. A theoretical lower bound implies that our circuits cannot be improved by more than a factor of two. We additionally