Searching for authors named Jaan Raik – sorted by Relevance.
32 documents found, showing 1 through 10.
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Enhancing hierarchical ATPG with a functional fault model for multiplexers
- …ENHANCING HIERARCHICAL ATPG WITH A FUNCTIONAL FAULT MODEL FOR MULTIPLEXERS Jaan Raik Raimund Ubar…
- Cited by 3 (0 self) – Add To MetaCart
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Multi-Valued Simulation with Binary Decision Diagrams
- …MULTI-VALUED SIMULATION WITH BINARY DECISION DIAGRAMS Raimund UBAR, Jaan RAIK Technical University…
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Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
- … Decision Diagram Representations JAAN RAIK AND RAIMUND UBAR Department of Computer Engineering, Tallinn…
- Cited by 17 (7 self) – Add To MetaCart
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Test Synthesis from Register-Transfer Level Descriptions
- …Test Synthesis from Register-Transfer Level Descriptions Jaan Raik, Priidu Paomets Electronics…
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High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation
- … Decision Diagram (DD) models where, differently from known Jaan Raik, Raimund Ubar Tallinn Technical…
- Cited by 4 (1 self) – Add To MetaCart
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Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams Adam Morawiec
- … Morawiec 1 , Raimund Ubar 2 , Jaan Raik 2 1 TIMA Laboratory, France; 2 Tallinn Technical University…
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Environment for Fault Simulation Acceleration on FPGA
- …Environment for Fault Simulation Acceleration on FPGA Peeter Ellervee, Jaan Raik, Valentin…
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Sequential Circuit Test Generation Using Decision Diagram Models
- … should not be a major issue. Jaan Raik, Raimund Ubar Department of Computer Engineering Tallinn Technical…
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High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation
- … coverage. However, as experiments show, for the given benchmark circuits this loss is minimal. Jaan Raik…
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Targeting Conditional Operations in Sequential Test Pattern Generation
- …]. Jaan Raik, Raimund Ubar Tallinn Technical University, Estonia Circuit PIs POs Path activation…
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