One way to provide fault isolation among cooperating software modules is to place each in its own address space. However, for tightly-coupled modules, this solution incurs prohibitive context switch overhead, In this paper, we present a software approach to implementing fault isolation within a

reclaims the pages considered least valuable by the operating system running in a virtual machine. An idle memory tax achieves efficient memory utilization while maintaining performance isolation guarantees. Content-based page sharing and hot I/O page remapping exploit transparent page remapping

for critical system state. XFI can be seen as a flexible, generalized form of software-based fault isolation (SFI). In the second part of this paper we present ISA support for XFI, in the form of simple bounds-check instructions. CFI and XFI can significantly increase the security and integrity of software

system or other applications. In this paper, we propose Harbor, a memory protection system that prevents many forms of memory corruption. We use software based fault isolation (“sandboxing”) to restrict application memory accesses and control flow to protection domains within the address space. A

approach and provides at-speed testing capability without any hardware or performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage

of Application Level Fault Tolerance (ALFT) over other software-based fault tolerance methods. We then develop sensible energyaware heuristics for ALFT schemes. The heuristics yield up to 40 % energy savings.

performance hindrance of high-speed external testers, Software-Based Self-Test (SBST) is proposed as a high-quality low-cost at-speed testing solution for AC failures in programmable processors and System-on-Chips (SoC). SBST utilizes low-cost testers, applies tests and captures test responses in the natural

. The proposed test method, i.e. mutation testing, allows us to work with a fault model at software level on VHDL descriptions; this approach has already shown its efficiency on combinational descriptions. In order to tackle the specific problem of sequential circuits, the description is modified so

show that BCube can be seamlessly integrated with the TCP/IP protocol stack and BCube packet forwarding can be efficiently implemented in both hardware and software. Experiments in our testbed demonstrate that BCube is fault tolerant and load balancing and it significantly accelerates representative

ABSTRACT Software-based path delay fault testing (SPDFT) has been used to identify faulty chips that cannot meet timing constraints due to gross delay defects. In this paper, we propose using SPDFT for a new purpose -aggressively selecting the operating point of a variation-affected design