"... In PAGE 8: ...etwork latencies. The reason is the following. The full software overhead (approximately 100 cycles) is only experienced by the first message to a processor. Subsequent messages experience latencies shown in Table2 . If the overhead of the first message was amortized across all messages, the average message latency statistics would certainly be higher.... In PAGE 9: ...28 27.26 Table2 : The effect of virtual circuit caching. Program (256 PEs) Non-VCC Latency VCC Latency 0.... ..."

"... In PAGE 8: ... This permits the students to safely explore and test control strategies on a fast simulator before implementing it on the actual process. In addition to the laboratory experiments, we have provided a few virtual experiments ( Table4 ). ... In PAGE 9: ... Virtual experiments can help overcome such drawbacks by enabling simulations of industrial processes that are too complex, unsafe or expensive to be built at laboratory scale. We have built additional virtual experiments including the Shell fractionator column simulation and the Tennessee Eastman (TE) problem (see Table4 ). The Shell fractionator column control problem has been used as a unifying example for comparison of feedforward, feedback, cascade, multi-loop, inferential, and multivariable control structures.... In PAGE 14: ... List of Experiments Table 3. Other MATLAB Tools Provided Table4... ..."

"... In PAGE 11: ... The numbers give an idea of how much more efficient a template-based implementation is. Table1 shows the results in column virtual. Virtual method calls cause a runtime overhead between 25% and 80%.... In PAGE 11: ... One important claim is that iterators are advantageous because they avoid temporary datastructures. Table1 shows in column temporary that computing temporary datastructures has limited impact on finite domain variables (about 3%), but considerable impact for set constraints (59% to 126% overhead). Temporary datastructures have been emulated by wrapping all iterators in a cache-iterator as described in Sect.... ..."

"... In PAGE 22: ... 5.3 Strategy for Selection of Virtualization Schemes Given block-cyclic distributions for A(m1 : n1) and B(m2 : n2), four choices are available for the virtualiza- tion scheme used, as shown in Table2 . The choice of the virtualization scheme depends on the additional indexing overhead per processor.... ..."

"... In PAGE 49: ... 4.1 Direct Access Path The direct VNI consists of a set of memory mapped registers shown in Figure 4-3, a set of atomic operations listed in Table4 -1 and a set of interrupts and traps listed in Table 4-2. The operations are implemented as instructions in FUGU but might be encoded as writes to additional memory-mapped registers.... In PAGE 50: ... elseif atomicity-extend is set then cause an atomicity-extend trap. else set UAC := (UAC ^ ( MASK)) Table4 -1. Direct virtual network interface operations.... In PAGE 52: ... See endatom in Table 4-1. Table4 -3. Detail of individual flags in the User Atomicity Control (UAC) register.... In PAGE 52: ... Control over user-level interrupts is implemented with four atomicity control bits in the User Atomicity Control (UAC) register which are manipulated via the beginatom and endatom operations. Table4 -3 details the individual flags in the UAC register. Two of the bits are modifiable only in kernel mode and are configured by the hardware or kernel code before giving control of the processor to the user.... In PAGE 52: ... The other two bits can be set and reset by the user via beginatom and endatom, respectively. Under certain conditions, noted in Table4 -1 (but generally whenever either of the kernel bits is set), endatom executed in user mode will trap to return control to the operating... In PAGE 55: ... The fast path in the direct virtual network interface can have performance close to unprotected messages in a single-user machine. To show the performance of the direct VNI, Table4 -4 details the cost of sending and receiving messages in FUGU at kernel level and at user level using two different atomicity mechanisms. The cycle counts are made from simulator traces of a simple ping-pong benchmark and the timings have been verified against the hardware.... In PAGE 55: ... The send side of the direct VNI always uses hardware. The send cost of seven cycles shown in Table4 -4 corresponds to a null message sent via a blocking inject operation. The receive cost is given two ways, corresponding to reception via an interrupt and reception via polling loop.... In PAGE 55: ... This sort of polling loop is useful in applications that orchestrate communication closely. The atomicity mechanism and GID manipulations are performed in software in the current system ( soft atomicity in Table4 -4). However, Table 4-4 also includes predictions of the performance expected using the revocable interrupt disable mechanism by eliminating the appropriate categories.... In PAGE 57: ...Cycles Minimum buffer-insert handler 180 Maximum handler (w/vmalloc) 3,162 Execute null handler from buffer 52 Overhead for an isolated null message about 1400 Table4 -5. Cycle counts for overhead to insert and extract messages from the software buffer.... In PAGE 57: ...imits the maximum observable messaging rate, as observed in Section 7.4.2. The implementation of the buffered path is evaluated using a microbenchmark that causes many messages to be buffered. The overheads, including allocation of virtual memory on demand, are tabulated in Table4 -5, listing the minimum and maximum buffer insertion times and the buffer extraction overhead. The minimum overhead per message is 232 (= 180 + 52) cycles, or about 2.... In PAGE 59: ... The major question is whether two-case delivery can provide a performance benefit over a system that simply always buffers messages. We have shown in this chapter ( Table4 -4) that the implementation of two-case delivery in FUGU achieves low-level message overheads near those of unprotected hardware. The primary experiment in Chapter 7 will show that fast-case performance is achievable over a useful range of mixed, multiprogrammed workloads expected in a scalable workstation.... In PAGE 60: ... The buffer enqueue handler overhead is important to system performance, as will be shown in detail in Chapter 7. The minimum buffer enqueue handler overhead of 180 cycles listed in Table4 -5 includes a user interrupt time. In another implementation of two-case delivery, the relative costs of operations could be quite different.... In PAGE 60: ... If a small amount of extra hardware were to be invested in FUGU, a good use would be a limited automatic DMA function to accelerate the most common case of buffer enqueue. The thread scheduling overheads in FUGU are abysmal, as revealed in the cost to receive an isolated message via the buffered path ( Table4 -5). Support for threads could be made as fast as 10s of cycles (as in the featherweight threads proposed in [40]).... In PAGE 65: ... Referring to Figure 5-2, in the fast, common case, (1), the message system runs at hardware speeds. Message reception overhead in the prototype is 115 cycles for a null message (from Table4 -4). When buffering is invoked, but physical space is available for buffer storage, every... In PAGE 66: ... message must pass through memory, (2), at a reduced rate. In the best case (no allocations and messages are handled in batches), the overhead per message received is about 232 cycles for a null message (the sum of 180 cycles insertion time and 52 cycles extract time from Table4 -5). A fresh page allocated and mapped by the operating system costs 3,162 cycles.... In PAGE 84: ...Microbenchmark results presented in Chapter 4 ( Table4 -4) show that the base message-passing costs in FUGU are comparable to the costs of an unprotected, direct interface on a single-user machine built on the same hardware base. Others have shown that tightly-coupled, direct interfaces tend to be more efficient than indirect, memory-based interfaces [28, 56].... In PAGE 88: ... For instance, according to Table 7-2, a process in an 8-processor configuration running enum receives a message every 953 cycles. From Table4 -4, the difference in overhead between our direct VNI implementation and unprotected, Alewife kernel messages on the same hardware is 115 ? 54 = 61 cycles. So, crudely, enum could be expected to run about 6% faster if we abandoned protection.... In PAGE 99: ...n the mixed workload model using interrupt-based delivery. There are three sets of numbers. The first set consists of the values measured from our direct VNI implementation (Tables 4-4 and 4-5) along with estimates for a range of costs with a hardware buffered system. The hardware buffering Odir cost is estimated to be the direct-path upcall cost in FUGU, plus 42 cycles to manipulate the queue (based on the queue extract cost in Table4 -5 minus a 10-cycle cache miss time), plus a cache miss time. Two numbers are given to represent a range of cache fill times from memory.... In PAGE 100: ... Estimates for hardware buffering are given as a pair based representing a range of main memory fill times of 10 cycles (in the actual FUGU hardware) to 200 cycles. cost of 52 cycles from Table4 -5. We assume, optimistically to both hardware- and software-based buffering, that any cache miss cost in the buffered case can be successfully amortized or tolerated over a batch of buffered messages.... In PAGE 100: ...hortly below and then again in Section 7.4.2. The second set of numbers in Table 7-4, presented here for comparison, are speculative estimates of overhead costs in a re-implementation of the direct VNI. The protected upcall in the direct case could be reduced from 115 cycles to 87 cycles using atomicity hardware, as shown in Table4 -4. Further, the common case of the queue insert interrupt handler could be speeded up significantly.... ..."