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Table 1. Bluetooth low-power mode measurements

in Heterogeneous wireless network management
by Wajahat Qadeer, Wajahat Qadeer, Tajana Simunic Rosing, Tajana Simunic Rosing, John Ankcorn, John Ankcorn, Venky Krishnan, Venky Krishnan, Givanni De Micheli, Givanni De Micheli 2003
"... In PAGE 5: ... They can be activated once a connection exists between Bluetooth devices. Transition times and average power dissipation for switching between the modes are shown in Table1 . The CSR Bluetooth chips also supports deep sleep state with only 270uW power consumption [15].... ..."
Cited by 3

Table 1. Bluetooth low-power mode measurements

in Heterogeneous wireless network management
by Wajahat Qadeer, Tajana Simunic Rosing, John Ankcorn, Venky Krishnan, Givanni De Micheli 2003
"... In PAGE 4: ... They can be activated once a connection exists between Bluetooth devices. Transition times and average power dissipation for switching between the modes are shown in Table1 . The CSR Bluetooth chips also supports deep sleep state with only 270uW power consumption [15].... ..."
Cited by 3

Table 1: Comparison of hardware cost and power consumption of the logarithmic low-power DCT architecture with other approaches.

in Algorithm-Based Low-Power Transform Coding Architectures - Part II: Logarithmic Complexity, Unified Architecture, and Finite-Precision Analysis
by An-yeu Wu, K. J. Ray Liu 1995
"... In PAGE 6: ...5 frequency at the nal stage, we need a total of (log M +2) multipliers to realize the multirate transfer function. The comparison of the logarithmic low-power architecture with other approaches is listed in Table1 . Although the total power savings of the logarithmic structure is less than that of the full multirate structure given the same decimation factor M, the O(log M) hardware overhead is preferable when we want to achieve low-power consumption without trading too much chip area.... ..."
Cited by 1

Table 1. Synthesis results of all components of the low-power SHA-256 module

in A Case Against Currently Used Hash Functions
by Martin Feldhofer, Christian Rechberger 2006
"... In PAGE 8: ...3 V. All presented results in Table1 come from simulations on transistor level using Nanosim from Synopsys. Perform- ing a hash calculation on a 512-bit block of data requires 1,128 clock cycles which is suitable for RFID communication protocols using interleaved proto- cols according to [5].... ..."
Cited by 11

Table 3: Power Optimizations for Mediabench Benchmarks. The columns indicate the speed decrease the power improvement, and the % nodes made low-power.

in Modeling the global critical path in concurrent systems
by Girish Venkataramani, Tiberiu Chelcea, Mihai Budiu, Seth C. Goldstein 2006
"... In PAGE 17: ... The algorithm stops when there are no candidates for optimization or all nodes have been inspected. We have conducted a preliminary study of the power optimization algorithm on the Mediabench kernels, and Table3 presents those that show some benefit. The low- power implementations are only 0.... ..."
Cited by 4

Table 3. Summary of localized and full chip power savings with low-power modes. Numbers shown are the maximum realizable power savings for each mode.

in Power and Energy Reduction Via Pipeline Balancing
by R. Iris Bahar 2001
"... In PAGE 7: ... Likewise, the 6X128 scheme produces a savings of BEBMBEB1 B7 BGBMBCB1 BP BIBMBEB1. Table3 summarizes the potential ener- gy savings calculated above for each component and configura- tion scheme. All values are rounded to the nearest whole number, and they represent the maximum power savings possible for the given configuration.... In PAGE 7: ... All values are rounded to the nearest whole number, and they represent the maximum power savings possible for the given configuration. The total power reduction for each program is a function of the numbers given in Table3 and the percent of execution time the program spends in each low-power mode. 4.... In PAGE 10: ....5. Full chip power and energy reduction Just as performance characteristics such as branch mispredic- tion rate or cache miss rate must be looked at in the context of their impact on overall performance, so should localized power results be placed in the context of full chip power. The approximate upper bound for power savings with PLB is shown in Table3 . The best case scenario is to execute in 4-wide mode all the time, resulting in a full chip power savings of 12%.... ..."
Cited by 77

Table 5.1: Tracking performance of the high-gain PID controller.

in Active learning in motor control
by Philipp Robbel 2005

TABLE 1. BLUETOOTH LOW-POWER MODE MEASUREMENTS OFF

in Heterogeneous wireless network management
by W. Qadeer, T. Simunic, J. Ankcorn, V. Krishnan, G. De Micheli 2003
Cited by 3

Table 1: Simulated Low-Power Neuron Performance

in Report to the National Science Foundation: WORKSHOP ON NEUROMORPHIC ENGINEERING
by Telluride Co, Avis Cohen, Shihab Shamma, Giacomo Indiveri, Tim Horiuchi, R. Douglas, C. Koch, T. Sejnowski 1999

Table 1 below): Low Power Option to Low Power Option, Standard to Low Power Option; Standard to

in unknown title
by unknown authors
"... In PAGE 4: ... UART Frame Figure 13b. IR Frame Tables Table1 . Link Distance Specifications Table 2.... In PAGE 10: .... A summary of pulse durations for all supported data rates appears in Table1 in Section 4.1.... In PAGE 12: ... Table1 . Link Distance Specifications The Bit Error Ratio (BER) shall be no greater than 10^-8.... In PAGE 34: ...2 kb/s operation; Tables 8 amp; 9, for the low power option (up to 115.2 kb/s); Table1 0, for 1.152 Mb/s; Table 11 for, 4.... ..."
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