Searching for authors named "Zhichun Zhu" – sorted by Relevance.
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A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
- A Performance Comparison of DRAM Memory System Optimizations for SMT Processors Zhichun Zhu Dept
- Cited by 16 (1 self) – Add To MetaCart
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Analysis of Commercial Workload on SMP Multiprocessors
- Analysis of Commercial Workload on SMP Multiprocessors Xiaodong Zhang a , Zhichun Zhu a
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Memory Hierarchy Considerations for Cost-Effective Cluster Computing
- @(email omitted); Xiaodong Zhang and Zhichun Zhu Department of Computer Science College of William and Mary Williamsburg, VA
- Cited by 2 (0 self) – Add To MetaCart
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Fine-grain Priority Scheduling on Multi-channel Memory Systems
- ), 2002 Fine-grain Priority Scheduling on Multi-channel Memory Systems Zhichun Zhu Zhao Zhang Xiaodong
- Cited by 7 (2 self) – Add To MetaCart
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Cached DRAM for ILP Processor Memory Access Latency Reduction
- 22 Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang College of William and Mary CACHED DRAM FOR ILP
- Cited by 6 (1 self) – Add To MetaCart
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A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality
- and Exploit Data Locality Zhao Zhang Zhichun Zhu Xiaodong Zhang Department of Computer Science College
- Cited by 29 (6 self) – Add To MetaCart
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DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
- , Hongzhong Zheng2 , Zhichun Zhu2 , Zhao Zhang1 and Howard David3 1 Department of Electrical 2 Department
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Thermal Modeling and Management of DRAM Memory Systems
- Thermal Modeling and Management of DRAM Memory Systems Jiang Lin 1 , Hongzhong Zheng 2 , Zhichun
- Cited by 3 (1 self) – Add To MetaCart
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AN ACCESS-MODE PREDICTION TECHNIQUE BASED ON CACHE HIT AND MISS SPECULATION FOR CACHE DESIGN ACHIEVES MINIMAL ENERGY CONSUMPTION. USING THIS METHOD, CACHE ACCESSES CAN BE ADAPTIVELY SWITCHED BETWEEN THE WAY-PREDICTION AND THE PHASED ACCESSING MODES.
- 58 ACCESS-MODE PREDICTIONS FOR LOW-POWER CACHE DESIGN Zhichun Zhu Xiaodong Zhang College
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Design and Optimization of Large Size and
- Size and Low Overhead Off-Chip Caches Zhao Zhang, Member, IEEE, Zhichun Zhu, Member, IEEE, and Xiaodong
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