Searching for authors named "Zeljko Zilic" – sorted by Relevance.
-
Galois Field Circuits and Realization of Multiple-Valued Logic Functions
- Galois Field Circuits and Realization of Multiple-Valued Logic Functions by Zeljko Zilic A thesis
- Add To MetaCart
-
An Overview of the QUALCOMM CDMA Digital Cellular Proposal
- 1 of 12 An Overview of the QUALCOMM CDMA Digital Cellular Proposal Zeljko Zilic ELE 1543S- Course
- Add To MetaCart
-
Current-mode CMOS Galois Field Circuits
- Current-mode CMOS Galois Field Circuits Zeljko Zilic and Zvonko Vranesic Department of Electrical
- Cited by 3 (0 self) – Add To MetaCart
-
Dynamic Clock Management for Low Power Applications in FPGAs
- Dynamic Clock Management for Low Power Applications in FPGAs Ian Brynjolfson and Zeljko Zilic
- Cited by 12 (0 self) – Add To MetaCart
-
A New Pll Design For Clock Management Applications
- A NEW PLL DESIGN FOR CLOCK MANAGEMENT APPLICATIONS Ian Brynjolfson and Zeljko Zilic Department
- Cited by 2 (1 self) – Add To MetaCart
-
FPGA Clock Management for Low Power
- FPGA Clock Management for Low Power Ian Brynjolfson and Zeljko Zilic Department of Electrical
- Cited by 2 (0 self) – Add To MetaCart
-
Identifying redundant wire replacements for synthesis and verification
- and Zeljko Zilic McGill University, Dept. of ECE {kasiar,zeljko}@(email omitted); ABSTRACT We propose
- Cited by 1 (0 self) – Add To MetaCart
-
Brief Contributions________________________________________________________________________________ A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields
- ________________________________________________________________________________ A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields Zeljko Zilic, Member
- Add To MetaCart
-
Adding debug enhancements to assertion checkers for hardware emulation and silicon debug
- Boulé, Jean-Samuel Chenard and Zeljko Zilic McGill University marc.boule@(email omitted);, {jsamch,zeljko
- Cited by 2 (1 self) – Add To MetaCart
-
Using BDDs to Design ULMs for FPGAs
- Using BDDs to Design ULMs for FPGAs Zeljko Zilic and Zvonko G. Vranesic University of Toronto
- Cited by 4 (0 self) – Add To MetaCart

