Searching for authors named "Zebo Peng" – sorted by Relevance.
98 documents found, showing 1 through 10.
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Application Specific Instruction Processor Architecture
- …Zebo Peng, ESLAB, LiTH ASIP Architecture 1 Application Specific Instruction Processor Architecture…
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Digital System Simulation with VHDL in a High-level Synthesis System
- … System Zebo Peng E-mail: zpe@(email omitted); Abstract This paper presents the use of VHDL to simulate…
- Cited by 4 (2 self) – Add To MetaCart
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Testability-Driven High-Level Synthesis
- …TESTABILITY-DRIVEN HIGH-LEVEL SYNTHESIS Zebo Peng Dept. of Computer and Information Science…
- Cited by 2 (1 self) – Add To MetaCart
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High-Level Test Synthesis Using Design Transformations
- … Zebo Peng E-mail: zebpe@(email omitted); Abstract A transformation-based approach to high-level test…
- Cited by 2 (1 self) – Add To MetaCart
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Inter-Domain Movement of Functionality as a Repartitioning Strategy for Hardware/Software Co-Design
- … Strategy for Hardware/Software Co-Design Erik Stoy and Zebo Peng E-mail: erist@(email omitted); Abstract…
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Design and Synthesis of a Generic Board-Level Test Controller
- …Design and Synthesis of a Generic Board-Level Test Controller Jan H��keg��rd and Zebo Peng Dept…
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Test Scheduling and Scan-Chain Division Under Power Constraint
- …Test Scheduling and Scan-Chain Division Under Power Constraint Erik Larsson and Zebo Peng…
- Cited by 17 (3 self) – Add To MetaCart
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A Technique for Test Infrastructure Design and Test Scheduling
- …ATECHNIQUEFORTESTINFRASTRUCTUREDESIGNANDTESTSCHEDULING Erik Larsson and Zebo Peng Department…
- Cited by 3 (0 self) – Add To MetaCart
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Integrated Scheduling and Allocation in High-Level Test Synthesis
- …1 Integrated Scheduling and Allocation in High-Level Test Synthesis Tianruo Yang, Zebo Peng…
- Cited by 1 (1 self) – Add To MetaCart
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System-on-chip test parallelization under power constraints
- …System-on-Chip Test Parallelization Under Power Constraints Erik Larsson and Zebo Peng Department…
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