Searching for authors named "Yasutaka Wada" – sorted by Relevance.
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Compiler control power saving scheme for multi core processors
- † , Yasutaka Wada † , Hiroaki Shikano ‡ , Keiji Kimura †‡ , and Hironori Kasahara †‡ † Dept. of Computer
- Cited by 2 (2 self) – Add To MetaCart
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Parallelizing compilation scheme for reduction of power consumption of chip multiprocessors
- Shirako 1 , Naoto Oshiyama 1 , Yasutaka Wada 1 , Hiroaki Shikano 2 , Keiji Kimura 1,2 , and Hironori
- Cited by 1 (1 self) – Add To MetaCart
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Multigrain parallel processing on compiler cooperative oscar chip multiprocessor architecture
- Multigrain Parallel Processing on Compiler Cooperative Chip Multiprocessor Keiji Kimura, Yasutaka
- Cited by 1 (0 self) – Add To MetaCart

