Searching for authors named "Xuejue Huang" – sorted by Relevance.
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Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
- Xuejue Huang, Phillip Restle 1 , Thomas Bucelot 1 , Yu Cao, and Tsu-Jae King EECS Department, University
- Cited by 5 (0 self) – Add To MetaCart
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A new analytical delay and noise model for on-chip RLC interconnect
- A New Analytical Delay and Noise Model for On-Chip RLC Interconnect Yu Cao, Xuejue Huang, Dennis
- Cited by 2 (0 self) – Add To MetaCart
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Sub-50 nm p-channel FinFET
- FET Xuejue Huang, Student Member, IEEE, Wen-Chin Lee, Charles Kuo, Digh Hisamoto, Member, IEEE, Leland Chang
- Cited by 4 (3 self) – Add To MetaCart
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RLC signal integrity analysis of high-speed global interconnects
- RLC Signal Integrity Analysis of High-Speed Global Interconnects Xuejue (Cathy) Huang, Yu Cao
- Cited by 2 (0 self) – Add To MetaCart
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Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Designs
- * Yu Cao 1 , Chenming Hu 1 , Xuejue Huang 1 , Andrew B. Kahng 2 , Sudhakar Muddu 3 , Dirk Stroobandt 4
- Cited by 7 (0 self) – Add To MetaCart
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Sub 50-nm FinFET: PMOS (revised 12/9/1999)
- Sub 50-nm FinFET: PMOS (revised 12/9/1999) Xuejue Huang, Wen-Chin Lee, Charles Kuo, Digh Hisamoto
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Improved A Priori Interconnect Predictions and Technology Extrapolation in the GTX System
- , 1 Chenming Hu, 1 Xuejue Huang, 1 Andrew B. Kahng, 2 Igor L. Markov, 3 Michael Oliver, Dirk
- Cited by 3 (0 self) – Add To MetaCart

