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Searching for authors named "Xiaoliang Bai" – sorted by Relevance.

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9 documents found, showing 1 through 9.

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Self-Test Methodology for AtSpeed Test of Crosstalk
by Xiaoliang Bai — 2000 — in Chip Interconnects,” in Proc. Design Automation Conf. (DAC’00
…Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects Xiaoliang Bai…
Cited by 18 (7 self) – Add To MetaCart

High-level Crosstalk Defect Simulation for System-on-Chip Interconnects
by Xiaoliang Bai, Sujit Dey — 2001
… significant in long interconnects [8] [9]. Therefore, it Xiaoliang Bai, Sujit Dey ECE Department UC San Diego…
Cited by 2 (2 self) – Add To MetaCart

Uncertainty-Aware Circuit Optimization
by Xiaoliang Bai University, Xiaoliang Bai, Philip N. Strenski — 2002
…Uncertainty-Aware Circuit Optimization Xiaoliang Bai University of California at San Diego La…
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Hyac: A Hybrid Structural SAT Based ATPG for Crosstalk
by Xiaoliang Bai, Sujit Dey, Angela Krstić — 2003 — In Proceedings IEEE VLSI Test Symposium (VTS
…HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk Xiaoliang Bai, Sujit Dey Dept. of ECE…
Cited by 1 (0 self) – Add To MetaCart

Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
by Xiaoliang Bai, Sujit Dey, Li Chen, Li Chen — 2001 — Processor Cores,” in Proc. Design Automation Conf. (DAC’01
…, Xiaoliang Bai, and Sujit Dey Dept. ECE, University of California at San Diego, La Jolla, CA 92093…
Cited by 7 (4 self) – Add To MetaCart

A STATIC NOISE IMPACT ANALYSIS METHODOLOGY FOR EVALUATING TRANSIENT ERROR EFFECTS IN DIGITAL VLSI CIRCUITS 1
by Chong Zhao, Xiaoliang Bai, Sujit Dey
… CIRCUITS 1 Chong Zhao, Xiaoliang Bai, Sujit Dey {chong, xibai, dey}@(email omitted); Department of Electrical…
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Noise-Aware Driver Modeling for Nanometer Technology
by Xiaoliang Bai, Rajit Ch, Sujit Dey, P. V. Srinivas — 2003 — IEEE International Symposium on Quality Electronic Design, ISQED'03
…Noise-Aware Driver Modeling for Nanometer Technology Xiaoliang Bai 1 , Rajit Chandra* 1 , Sujit…
Cited by 2 (0 self) – Add To MetaCart

Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits
by Xiaoliang Bai, Rajit Ch, Sujit Dey, Prasanna V. Srinivas — 2004 — IEEE Transactions on Computer-Aided Design
…_______________________________________________________________________________ Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits Xiaoliang Bai…
Cited by 1 (0 self) – Add To MetaCart

Uncertainty-Aware Circuit Optimization
by Xiaoliang Bai Ece, Xiaoliang Bai, Chandu Visweswariah, Philip N. Strenski, David J. Hathaway — 2002 — In DAC
…Uncertainty-Aware Circuit Optimization Xiaoliang Bai ECE Dept. UC San Diego La Jolla, CA 92037…
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Showing 1 through 9.

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