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Searching for authors named "Waleed Meleis" – sorted by Relevance.

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  • Operating System Impact on Trace-Driven Simulation  
  • by Jason Casmira, John Fraser, David Kaeli, Waleed Meleis — 1998 — Proc. of the 31st Annual Simulation Symposium
  • …Trace-driven simulation is commonly used by the computer architecture research community to pursue answers to a wide variety of architectural design issues. Traces taken from benchmark execution have been extensively studied to optimize the design of pipelines, branch predictors, and especially cach…
  • Cited by 5 (2 self) – Add To MetaCart
  • DSPTune: A Performance Evaluation Toolset for the SHARC Signal Processor  
  • by Suleyman Sair, David Kaeli, Waleed Meleis — 1999 — the 3rd Annual Workshop on High Performance Embedded Computing
  • …Performance tuning in the embedded systems domain poses a new set of challenges for software and hardware designers. Techniques proven to work for general purpose architectures can not always be directly applied to the signal processor environment. Program analysis tools have been shown to be invalu…
  • Cited by 1 (1 self) – Add To MetaCart
  • Optimal Local Register Allocation for a Multiple-Issue Machine  
  • by Waleed Meleis, Edward S. Davidson — 1994 — In Proceedings of the 8th international conference on Supercomputing
  • …This paper presents an algorithm that allocates registers optimally for straight-line code running on a generic multi-issue computer. On such a machine, an optimal register allocation is one that minimizes the number of issue slots that the code requires. Optimal spill selection and load/store place…
  • Cited by 6 (0 self) – Add To MetaCart
  • Dual-Issue Scheduling With Spills For Binary Trees  
  • by Waleed M. Meleis, Edward S. Davidson — 1999 — In Proceedings of the Tenth Annual ACM-SIAM Symposium on Discrete Algorithms
  • …We describe an algorithm that finds a minimum cost schedule, including spill code, for a register-constrained machine that can issue up to one arithmetic operation and one memory access operation at a time, under the restrictions that the dependence graph is a full binary tree, and all operations ha…
  • Cited by 1 (0 self) – Add To MetaCart
  • Balance Scheduling: Weighting Branch Tradeoffs in Superblocks  
  • by Alexandre E. Eichenberger, Waleed M. Meleis — in Superblocks”, Proc. 32 nd Ann. Int’l Symp. Microarchitecture (MICRO32
  • …Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superblocks. This is difficult in general because each branch competes for the processor's limited resources. Previous work manage…
  • Cited by 14 (3 self) – Add To MetaCart
  • A Study of Loop Unrolling for VLIW-based DSP Processors  
  • by Suleyman Sair David, David R. Kaeli, Waleed Meleis — 1998 — Proceedings of the Workshop on Signal Processing Systems
  • …With the growing popularity of DSPs and their associated applications, cost-effective software development has become a major issue. High-level language compilers are becoming more commonplace in the DSP world. While these compilers can generate correct code for DSP architectures, there remains c…
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  • Optimal Local Register Allocation for a Multiple-Issue Machine  
  • by Waleed Meleis Edward, Edward S. Davidson — 1994 — In Proceedings of the 8th international conference on Supercomputing
  • …This paper presents an algorithm that allocates registers optimally for straight-line code running on a generic multi-issue computer. On such a machine, an optimal register allocation is one that minimizes the number of issue slots that the code requires. Optimal spill selection and load/store place…
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  • Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance  
  • by John Kalamatianos, Alireza Khalafi, David R. Kaeli, Waleed Meleis — 1999 — IEEE Transactions on Computers
  • …In this paper we examine temporal-based program interaction in order to improve layout by reducing the probability that program units will conflict in an instruction cache. In that context, we present two profile-guided procedure reordering algorithms. Both techniques use cache line coloring to arri…
  • Cited by 4 (1 self) – Add To MetaCart
  • Lower Bounds on Precedence-Constrained Scheduling for Parallel Processors  
  • by Ivan D. Baev, Waleed M. Meleis, Alexandre Eichenberger — 2000 — Proc. the 29th Int’l Conf. Parallel Processing
  • …We consider two general precedence-constrained scheduling problems that have wide applicability in the areas of parallel processing, high performance compiling, and digital system synthesis. These problems are intractable so it is important to be able to compute tight bounds on their solutions. A ti…
  • Cited by 2 (0 self) – Add To MetaCart
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