Searching for "Transaction Level Error Susceptibility Model for Bus Based SoC Architectures." – sorted by Relevance.

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Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
by Lin Srinivasan Vijaykrishnan, I. -c. Lin, S. Srinivasan, N. Vijaykrishnan — 2006
…Transaction Level Error Susceptibility Model for Bus Based SoC Architectures I.-C. Lin, S…
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