Searching for authors named "Tony Givargis" – sorted by Relevance.
42 documents found, showing 1 through 10.
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Improved indexing for cache miss reduction in embedded systems
- …The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved performance. In traditional cache design, the index portion of the memory address bus consists of the K least significant bits…
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Zero cost indexing for improved processor cache performance
- …The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved performance. In traditional cache design, the index portion of the memory address bus consists of the K least significant bits…
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Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms
- …System-on-a-chip platform manufacturers are increasingly adding configurable features that provide power and performance flexibility, in order to increase a platform's applicability to a variety of embedded computing systems. We illustrate the energy benefits of combining the configurable features o…
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The Case for a Configure-and-Execute Paradigm
- …Tomorrow's silicon chips will hold more transistors tha most embedded system designers could possibly use under the prevalent "describe-and-synthesize" design paradigm, Many have thus re-proposed the once popular "capture-and-simulate" paradigm, wherein pre-designed Intellectual Property software an…
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Software virtual memory management for MMU-less embedded systems
- …For an embedded system designer, the rise in processing speeds of embedded processors and micro-controller evolution has lead to the possibility of running computation and data intensive applications on small embedded devices that earlier only ran on desktop-class systems. From a memory stand point,…
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Incorporating Cores into System-Level Specification
- …We describe an approach for incorporating cores into a system-level specification. The goal is to allow a designer to specify both custom behavior and pre-designed cores at the earliest design stages, and to refine both into implementations in a unified manner. The approach is based on experience wi…
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Differential GPS Reference Station Algorithm - Design And Analysis
- …The global positioning system (GPS) allows properly equipped users to determine their position based on the measured pseudoranges to at least four satellites. Differential GPS operation (DGPS) uses a reference station at a known location to calculate and broadcast pseudorange corrections to local us…
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Experimental Differential GPS Reference Station Evaluation
- …Differential GPS operation (DGPS) uses a reference station at a known location to calculate and broadcast pseudorange corrections to local users, resulting in improved user position accuracy. DGPS accuracy is limited by the ability of the reference station to remove the effects of receiver measureme…
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Cache Optimization for Embedded Processor Cores: An Analytical Approach
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Reference Caching Using Unit Distance Redundant Codes for Activity Reduction on Address Buses
- …Switching activity on I/0 pins of a chip is a measurable contributor to the total energy consumption of the chip. In this' work, we present an encoding mechanism that reduces switching activity of external address buses by combining an address reference caching mechanism with Unit Distance Redundant…
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