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Searching for "Timed Verification of Asynchronous Circuits." – sorted by Relevance.

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  • On the GALS Design Methodology of ETH Zurich  
  • by F. K. Gürkaynak, S. Oetiker, T. Villiger, N. Felber, H. Kaeslin, W. Fichtner — 2003 — FMGALS Workshop at the 12th International FME Symposium
  • verification Asynchronous circuits require certain timing conditions to hold for correct operation…
  • Cited by 1 (0 self)Add To MetaCart
  • Timing Analysis for Extended Burst-Mode Circuits  
  • by Supratik Chakraborty, David L. Dill, Kenneth Y. Yun, Kun-yung Chang — 1997 — In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
  • … [12] are two well-known techniques for hazard detection and timing verification of asynchronous
  • Cited by 12 (7 self)Add To MetaCart
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