Searching for "Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect." – sorted by Relevance.
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Test Pattern Generation and Partial-Scan Methodology for an Asynchronous SoC Interconnect
- IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. X, NO. X, MONTH 200X 1 Test Pattern Generation and Partial-Scan
- Cited by 2 (0 self) – Add To MetaCart

