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Test infrastructure design for mixed-signal SOCs with wrapped analog cores
by Anuja Sehgal, Student Member, Sule Ozev, Krishnendu Chakrabarty, Senior Member — 2006 — IEEE Trans. on Very Large Scale Integration (VLSI) Systems
… Test Infrastructure Design for Mixed-Signal SOCs With Wrapped Analog Cores Anuja Sehgal, Student Member…
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