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Test Time Reduction Reusing Multiple Processors in a Networkon-Chip Based Architecture
by Re M. Amory, Marcelo Lubaszewski, O G. Moraes, Edson I. Moreno — 2005 — Proceedings. . . [S.l.: s.n
…Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture Alexandre…
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