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Searching for authors named "Tejas Karkhanis" – sorted by Relevance.

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  • A Day in the Life of a Data Cache Miss  
  • by Tejas Karkhanis, J. E. Smith — 2002 — In Workshop on Memory Performance Issues
  • …The activity within a processor following a cache miss is studied via a series of simulation experiments. This is a preliminary step toward developing ways of mitigating data cache miss penalties, especially for long misses. With a modest -sized reorder buffer (ROB) of 64 entries, structural blockag…
  • Cited by 29 (2 self) – Add To MetaCart
  • Saving Energy with Just In Time Instruction Delivery  
  • by Tejas Karkhanis, James E Smith, Pradip Bose — 2002 — In Proceedings of the 2002 International Symposium on Low Power Electronics and Design
  • …Just-In-Time instruction delivery is a general method for saving energy in a microprocessor by dynamically limiting the number of in-flight instructions. The goal is to save energy by 1) fetching valid instructions no sooner than necessary, avoiding cycles stalled in the pipeline -- especially the i…
  • Cited by 19 (1 self) – Add To MetaCart
  • A Performance Counter Architecture for Computing Accurate  
  • by Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith — 2006 — CPI Components,” Architectural Support For Programming Languages and Operating Systems
  • …Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaining insight into the behavior of an application on a given microprocessor; consequently, they are widely used by software …
  • Cited by 3 (0 self) – Add To MetaCart
  • Energy efficient co-adaptive instruction fetch and issue  
  • by Alper Buyuktosunoglu, Tejas Karkhanis Y, David H. Albonesi, Pradip Bose Z — 2003 — In ISCA ’03: Proceedings of the 30th Annual International Symposium on Computer Architecture
  • …Front-end instruction delivery accounts for a significant fraction of the energy consumed in a dynamic superscalar processor. The issue queue in these processors serves two crucial roles: it bridges the front and back ends of the processor and serves as the window of instructions for the outof-order…
  • Cited by 21 (1 self) – Add To MetaCart
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