Searching for authors named "Stylianos Perissakis" – sorted by Relevance.

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7 documents found, showing 1 through 7.

Embedded DRAM for a Reconfigurable Array
by Stylianos Perissakis, Yangsung Joo, Jinhong Ahn, John Wawrzynek — 1999 — in Proceedings of the 1999 Symposium on VLSI Circuits
…A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 s, and application data memory,…
Cited by 8 (3 self) – Add To MetaCart

The Energy Efficiency of IRAM Architectures
by Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce Mcgaughy, David Patterson, Tom Anderson, Katherine Yelick — 1997 — In the 24th Annual International Symposium on Computer Architecture
…Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more energy efficient than conventional systems. The high density of DRAM permits a much larger amount of memory on-chip than a …
Cited by 31 (4 self) – Add To MetaCart

Scaling Processors to 1 Billion Transistors and Beyond: IRAM
by Stylianos Perissakis, Christoforos Kozyrakis, Tom Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, Kimberly Keeton, Dave Patterson, Randi Thomas, I Thomas, Kathy Yelick
…this paper we introduce an alternative way of using the huge amount of real estate available on such a chip: integrating the processor and the main memory on the same die. We call this architecture IRAM, for Intelligent RAM. Limitations of Conventional Architectures…
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Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures
by David Patterson Krste, David Patterson, Krste Asanovic, Aaron Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos Kozyrakis, David Martin, Stylianos Perissakis, I Thomas, Noah Treuhaft, Katherine Yelick — In Proceedings of the International Conference on Computer Design (ISCA 97
…The goal of Intelligent RAM (IRAM) is to design a cost-effective computer by designing a processor in a memory fabrication process, instead of in a conventional logic fabrication process, and include memory on-chip. To design a processor in a DRAM process one must learn about the business and cultu…
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Scalable Processors in the Billion-Transistor Era: IRAM
by Christoforos E. Kozyrakis, Stylianos Perissakis, David Patterson, Thomas Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, E. Kozyrakis, Benjamin Gribstad, Kimberly Keeton, Randi Thomas, Noah Treuhaft, Katherine Yelick, Jason Golbus — 1997
…ther architecture alternatives, like wide superscalar and VLIW (very long instruction word), suffer from drawbacks---implementation complexity, low utilization of resources, and immature compiler technology ---or deliver only modest performance improve-- ments. Moreover, they usually exacerbate the …
Cited by 35 (2 self) – Add To MetaCart

Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures
by David Patterson, Krste Asanovic, Aaron Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos Kozyrakis, David Martin, Stylianos Perissakis, Randi Thomas, Noah, I Thomas, Noah Treuhaft, Katherine Yelick — In Proceedings of the International Conference on Computer Design (ISCA 97
…The goal of Intelligent RAM (IRAM) is to design a cost-effective computer by designing a processor in a memory fabrication process, instead of in a conventional logic fabrication process, and include memory on-chip. To design a processor in a DRAM process one must learn about the business and cultur…
Cited by 4 (0 self) – Add To MetaCart

References Vectors and Streams
by Lecturer Melvyn Lim, Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo Lopez, Peter R. Mattson, John D. Owens, Width-efficient Architecture, Christoforos E. Kozyrakis, Stylianos Perissakis, David Patterson, Thomas Anderson, Kriste Asanovic, Neal Cardwell, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, I Thomas, Katherine Yelick, Scalable Processors — 2000
…Up to now, we have only looked at techniques that exploit instruction level parallelism to increase single-thread processor performance. The instruction level parallelism dictates how many instructions can be issued at the same time, and is limited by the amount of data dependencies among instructio…
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