MetaCart Sign in to MyCiteSeerX

Documents
Authors
Tables !

Searching for authors named "Steven Wallace" – sorted by Relevance.

Order by: Citations | Year (Descending) | Year (Ascending) | Recency

Try your query at: Scholar | Yahoo! | Ask | Bing | CSB

17 documents found, showing 1 through 10. Next 10 →

ATOM

SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance Abstract
by Steven Wallace
…SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance Abstract Steven Wallace…
Cited by 1 (0 self) – Add To MetaCart

A Scalable Register File Architecture for Dynamically Scheduled Processors
by Steven Wallace, Steven Wallace, Nader Bagherzadeh, Nader Bagherzadeh — 1996 — In International Conference on Parallel Architectures and Compilation Techniques
…A Scalable Register File Architecture for Dynamically Scheduled Processors Steven Wallace…
Cited by 49 (0 self) – Add To MetaCart

Instruction Fetching Mechanisms for Superscalar Microprocessors
by Steven Wallace, Nader Bagherzadeh — 1996 — In Proceedings of EURO-PAR'96
…Instruction Fetching Mechanisms for Superscalar Microprocessors Steven Wallace and Nader…
Cited by 2 (0 self) – Add To MetaCart

Multiple branch and block prediction
by Steven Wallace, Nader Bagherzadeh, Steven Wallace, Nader Bagherzadeh — 1997 — in Proceedings of the 1997 ACM/IEEE Conference on High Performance Computer Architecture
…Multiple Branch and Block Prediction Steven Wallace and Nader Bagherzadeh Department of Electrical…
Cited by 9 (0 self) – Add To MetaCart

Design and Implementation of a 100 MHz Centralized Instruction Window for a Superscalar Microprocessor
by Steven Wallace Nirav, Steven Wallace, Nirav Dagli, Nader Bagherzadeh
… Microprocessor Steven Wallace, Nirav Dagli, and Nader Bagherzadeh Department of Electrical and Computer…
Add To MetaCart

Performance Issues Of A Superscalar
by Microprocessor Steven Wallace, Steven Wallace, Nader Bagherzadeh — 1994 — In Proceedings of the 1994 International Conference on Parallel Processing
…PERFORMANCE ISSUES OF A SUPERSCALAR MICROPROCESSOR Steven Wallace and Nader Bagherzadeh…
Add To MetaCart

Threaded Multiple Path Execution
by Steven Wallace Brad — 1998
…-dependent on relatively Threaded Multiple Path Execution Steven Wallace Brad Calder Dean M. Tullsen Department of Computer…
Add To MetaCart

Performance Analysis of a Superscalar Architecture
by Steven Daniel Wallace, Steven Daniel Wallace — 1993
… by Steven Daniel Wallace Committee in charge: Professor Nader Bagherzadeh, Chair Professor Daniel Gajski…
Cited by 3 (2 self) – Add To MetaCart

A 20MHz CMOS Reorder Buffer for a Superscalar Microprocessor
by John Lenell, Steven Wallace, Nader Bagherzadeh
… Steven Wallace and Nader Bagherzadeh Department of Electrical and Computer Engineering University…
Cited by 3 (2 self) – Add To MetaCart

Design and Implementation of a 100 MHz Reorder Buffer
by Steven Wallace, Nirav Dagli, Nader Bagherzadeh — 1994 — In 37 t h Midwest Sympsium on Circuits and Systems
…Design and Implementation of a 100 MHz Reorder Buffer Steven Wallace, Nirav Dagli, and Nader…
Cited by 4 (2 self) – Add To MetaCart

Showing 1 through 10. Next 10 →

ATOM

Try your query at: Scholar | Yahoo! | Ask | Bing | CSB