Searching for authors named "Stefanos Kaxiras" – sorted by Relevance.
33 documents found, showing 1 through 10.
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Identification And Optimization Of Sharing Patterns For Scalable Shared-Memory Multiprocessors
- …Distributed shared-memory architectures typically employ a directory-based protocol to maintain cache coherence. Identifying sharing patterns in parallel programs and applying specialized optimizations can increase cache-coherence protocol efficiency and yield performance improvements. In this thesi…
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Kiloprocessor Extensions to SCI
- …To expand the Scalable Coherent Interface's (SCI) capabilities so it can be used to efficiently handle sharing in systems of hundreds or even thousands of processors, the SCI working group is developing the Kiloprocessor Extensions to SCI. In this paper we describe the proposed GLOW and STEM kilopro…
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4T-Decay Sensors : A New Class of Small, Fast
- …We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cells to measure on-chip temperature and leakage.Using the dependence of leakage currents to temperature, we measure varying …
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Ipstash: A power-efficient memory architecture for ip-lookup
- …High-speed routers often use commodity, fullyassociative,…
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Improving CC-NUMA performance using instruction-based prediction
- …We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior of load and store instructions in relation to coherent events and predicting their future behavior. Although this techniqu…
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Ipstash: A set-associative memory approach for efficient ip-lookup
- …Abstract—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hardware solutions such as TCAMs (Ternary Content Addressable Memories), despite their high power consumption, low upd…
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Kaxiras@cs.wisc.edu
- …In this paper we propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior of load and store instructions in relation to coherent events and predicting their future behavior. Although…
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Distributed Vector Architecture: Fine Grain Parallelism with Efficient Communication
- …Abstract—As processing power continues to increase while memory access latency and bandwidth become serious bottlenecks, processors and DRAM memory will be packaged increasingly tighter together, possibly on a single chip. This integration would introduce orders of magnitude superior bandwidth/laten…
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Coherence Communication Prediction in Shared-Memory Multiprocessors
- …Abstract—Sharing patterns in shared-memory multiprocessors are the key to performance: uniprocessor latencytolerating techniques such as out-of-order execution and non-blocking caches have proved unable to completely hide the latency of remote memory access. Recently proposed prediction mechanisms a…
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Comparing Power Consumption of an SMT and a CMP DSP for Mobile Phone Workloads
- …In the DSP world, many media workloads have to perform a specific amount of work in a specific period of time. This observation led us to examine Simultaneous Multithreading (SMT) and Chip Multiprocessing (CMP) for a VLIW DSP architecture (specifically the Star*Core SC140), in conjunction with Frequ…
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