Searching for "Special Section on VLSI Design and CAD Algorithms." – sorted by Relevance.
19 documents found, showing 1 through 10.
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Parallel Test Structure in Latch Based Asynchronous Pipeline
- …IEICE TRANS. FUNDAMENTALS, VOL.E82--A, NO.11 NOVEMBER 1999 2527 LETTER Special Section on VLSI…
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Improving Dictionary-Based Code Compression in VLIW Architectures
- …2318 IEICE TRANS. FUNDAMENTALS, VOL.E82--A, NO.11 NOVEMBER 1999 PAPER Special Section on VLSI…
- Cited by 7 (0 self) – Add To MetaCart
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A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths
- … Design and CAD Algorithms A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths Susumu…
- Cited by 4 (0 self) – Add To MetaCart
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High-level Synthesis of Pipelined Circuits from Modular Queue-Based Specifications
- …IEICE TRANS. FUNDAMENTALS, VOL.E84{A, NO.11 NOVEMBER 2001 1 PAPER Special Section on VLSI Design…
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Performance Evaluation of STRON: A Hardware Implementation of a Real-Time OS
- …IEICE TRANS. FUNDAMENTALS, VOL.E82--A, NO.11 NOVEMBER 1999 2375 PAPER Special Section on VLSI…
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SUMMARY
- … IEICE TRANS. FUNDAMENTALS, VOL.E84-A, NO.11 NOVEMBER 2001 1 PAPER Special Section on VLSI…
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A Proposition on Floating Gate Neuron MOS Macromodeling for Device Fabrications
- …IEICE TRANS. FUNDAMENTALS, VOL.E82--A, NO.11 NOVEMBER 1999 2485 PAPER Special Section on VLSI…
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A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops
- …2514 IEICE TRANS. FUNDAMENTALS, VOL.E82--A, NO.11 NOVEMBER 1999 PAPER Special Section on VLSI…
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The Controlling Value Boolean Matching
- …IEICE TRANS. FUNDAMENTALS, VOL. E00{A, NO. 10 OCTOBER 1996 PAPER Special Section on VLSI Design…
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Compact Representations of Logic Functions Using Heterogeneous MDDs
- …3168 IEICE TRANS. FUNDAMENTALS, VOL.E86--A, NO.12 DECEMBER 2003 PAPER Special Section on VLSI…
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