Searching for "Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction." – sorted by Relevance.

Order by: Citations | Year (Descending) | Year (Ascending) | Recency

Try your query at: Scholar | Yahoo! | Ask | Bing | CSB

1 documents found, showing 1 through 1.

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
by Yu Hu, Lei He, Tim Tuan — 2006 — in Proc. Design Automation Conf
…30.4 Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction ∗ ABSTRACT…
Cited by 2 (0 self) – Add To MetaCart

Showing 1 through 1.

Try your query at: Scholar | Yahoo! | Ask | Bing | CSB