Searching for authors named "Satrajit Chatterjee" – sorted by Relevance.
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BOOST: Berkeley’s Out-of-Order Stack Thingy
- BOOST: Berkeley’s Out-of-Order Stack Thingy Steve Sinha, Satrajit Chatterjee and Kaushik Ravindran
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DAG-aware AIG rewriting: A fresh look at combinational logic synthesis
- DAG-Aware AIG Rewriting A Fresh Look at Combinational Logic Synthesis Alan Mishchenko Satrajit
- Cited by 27 (13 self) – Add To MetaCart
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Improvements to combinational equivalence checking
- Improvements to Combinational Equivalence Checking Alan Mishchenko Satrajit Chatterjee Robert
- Cited by 17 (8 self) – Add To MetaCart
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An integrated technology mapping environment
- An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton
- Cited by 6 (2 self) – Add To MetaCart
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Factor Cuts
- ABSTRACT Factor Cuts Satrajit Chatterjee Alan Mishchenko Robert Brayton Enumeration of bounded
- Cited by 2 (1 self) – Add To MetaCart
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Improvements to Technology Mapping for LUT-based FPGAs
- Improvements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert
- Cited by 11 (7 self) – Add To MetaCart
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Integrating logic synthesis, technology mapping, and retiming
- Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee
- Cited by 7 (4 self) – Add To MetaCart
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FRAIGs: A unifying representation for logic synthesis and verification
- FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit
- Cited by 21 (7 self) – Add To MetaCart
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An Integrated Technology Mapping Environment
- An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton
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Integrating Logic Synthesis, Technology Mapping, and Retiming
- Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee
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