Searching for authors named "Satnam Singh" – sorted by Relevance.
26 documents found, showing 1 through 10.
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A Demonstration of Co-Design and Co-Verification in a Synchronous Language
- … Singh Xilinx Inc. 2100 Logic Drive, San Jose, CA95124, USA. Satnam.Singh@(email omitted); acute now…
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Architectural Descriptions for FPGA Circuits
- …Architectural Descriptions for FPGA Circuits Satnam Singh Dept. Computing Science The University…
- Cited by 19 (9 self) – Add To MetaCart
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Accelerating Adobe Photoshop with Reconfigurable Logic
- …Accelerating Adobe Photoshop with Reconfigurable Logic Satnam Singh Xilinx Inc. San Jose…
- Cited by 13 (1 self) – Add To MetaCart
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Implementing Fudgets with Standard Widget Sets
- …Implementing Fudgets with Standard Widget Sets Alastair Reid & Satnam Singh Computing Science…
- Cited by 10 (1 self) – Add To MetaCart
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Dynamic specialisation of XC6200 FPGAs by partial evaluation
- …Dynamic Specialisation of XC6200 FPGAs by Partial Evaluation Nicholas McKay 1 and Satnam Singh 2 1…
- Cited by 11 (3 self) – Add To MetaCart
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Debugging Techniques for Dynamically Reconfigurable Hardware
- …, we made extensive use of a logic analyser which gave us detailed run-time information. Satnam Singh…
- Cited by 5 (0 self) – Add To MetaCart
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Bezier Curve Rendering on Virtex(tm)
- …RAM is to simply to directly encode Satnam Singh and Robert Slous Xilinx Inc. San Jose, California, U.S.A. Satnam.Singh…
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System Level Specification in Lava
- …-1591/03 $17.00 © 2003 IEEE System Level Specification in Lava Satnam Singh Xilinx Inc. 2100 Logic Drive, San…
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Lava and JBits: From HDL to Bitstream in Seconds
- …. Satnam Singh and Phil James-Roxby Xilinx Inc. San Jose, California 95124, U.S.A. {Satnam.Singh, Phil…
- Cited by 6 (0 self) – Add To MetaCart
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The Design and Verification of a Sorter Core
- …The Design and Veri cation of a Sorter Core Koen Claessen 1 , Mary Sheeran 1 , and Satnam Singh 2…
- Cited by 3 (2 self) – Add To MetaCart
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