Searching for authors named "Rudy Lauwereins" – sorted by Relevance.
-
Implementation of a robust 3D-image reconstruction algorithm on a TMS320C67x DSP
- This paper describes optimisations done on the implementation of a metric 3D-image reconstruction algorithm on a TMS320C6701 DSP. From the optimised code, an abstraction is made for a description on a higher level. The algorithm takes a series of uncalibrated 2D images taken with a handheld camera a
- Add To MetaCart
-
Powerful High-Level Debugger for Parallel Programs
- The testing and debugging of complex programs has always been one of the most cost-determining factors in software design. This is even more true when parallel programs are considered. Debugging them is often based on a debugging cycle. First we make an assumption about the probable source of the bu
- Cited by 3 (2 self) – Add To MetaCart
-
The Consistent File-Status in a User-Triggered Checkpointing Approach
- The user-triggered checkpointing tool implements a non-blocking, co-ordinated (global) checkpointing method, where the programmer defines the contents and the position of the recovery-line. Within this tool, we developed and implemented file-checkpointing. This allows to include the status of files
- Cited by 3 (2 self) – Add To MetaCart
-
Close Approximations of Sigmoid Functions by Sum of Steps for VLSI Implementation of Neural Networks
-
This paper is devoted to show that there are simple and accurate ways to compute a sigmoid nonlinearity and its derivative in digital hardware by sum of steps, and that threshold gate implementation of such algorithms are area-efficient when compared to other known methods.
1. OVERVIEW - Cited by 3 (1 self) – Add To MetaCart
-
PDG: A Process-Level Debugger for Concurrent Programs in the GRAPE Parallel Programming Environment.
- In this paper, we describe the process-level debugger of GRAPE, our hierarchical graphical programming environment for concurrent programs. Its unique feature is that it clearly separates the identification of erroneous processes, which we call process-level debugging, from the exact localisation of
- Cited by 7 (3 self) – Add To MetaCart
-
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
- The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the existence of a deadlock free schedule. The presented algorithm fits in the design flow of GRAPE, an environment for the
- Cited by 7 (0 self) – Add To MetaCart
-
Systematic data reuse exploration methodology for irregular access patterns
- Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in embedded data dominated applications. Only recently effective formalized techniques to deal with this specific task have
- Cited by 1 (1 self) – Add To MetaCart
-
Rapid Prototyping of Digital Signal Processing Systems with GRAPE-II
- The paper describes GRAPE-II (Graphical RApid Prototyping Environment), an advanced system level development environment for the specification, compilation, debugging, simulation and emulation of Digital Signal Processing (DSP) applications. GRAPE-II supports the real-time emulation of synchronous m
- Cited by 1 (0 self) – Add To MetaCart
-
GRAPE-II: Graphical RApid Prototyping Environment for Digital Signal Processing Systems.
- The paper describes GRAPE-II (Graphical RApid Prototyping Environment), an advanced system level development environment for the specification, compilation, debugging, simulation and emulation of complete DSP applications. GRAPE-II fully supports the real-time emulation of synchronous multi-rate ap
- Cited by 2 (0 self) – Add To MetaCart
-
Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking On FPGAs
- Multimedia support appears on embedded platforms, such as WAP for mobile phones. However, true multimedia applications require both the computation power that only dedicated hardware can provide and the flexibility of software implementations. To this end, we are investigating reconfigurable archite
- Cited by 28 (7 self) – Add To MetaCart

