Searching for "Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order." – sorted by Relevance.

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Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions
by J. Stark, Jared Stark, Paul Racunas, Yale N. Patt — 1997 — In Proceedings of the 30th International Symposium on Microarchitecture
… contains all the research that looks at reducing the impact of instruction cache misses. Out-of-order issue…
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